uart16750.map.rpt

Implements a 16550/16750 UART core

; CState.bit5  ; 0            ; 0           ; 0          ; 0           ; 0           ; 1           ; 0           ; 0           ; 0           ; 0           ; 0           ; 0            ; 1           ;
; CState.bit6  ; 0            ; 0           ; 0          ; 0           ; 1           ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ; 0            ; 1           ;
; CState.bit7  ; 0            ; 0           ; 0          ; 1           ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ; 0            ; 1           ;
; CState.par   ; 0            ; 0           ; 1          ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ; 0            ; 1           ;
; CState.stop  ; 0            ; 1           ; 0          ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ; 0            ; 1           ;
; CState.stop2 ; 1            ; 0           ; 0          ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ; 0            ; 1           ;
+--------------+--------------+-------------+------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+--------------+-------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 293   ;
; Number of registers using Synchronous Clear  ; 42    ;
; Number of registers using Synchronous Load   ; 34    ;
; Number of registers using Asynchronous Clear ; 232   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 120   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------------------------------------------------------+
; Inverted Register Statistics                              ;
+-------------------------------------------------+---------+
; Inverted Register                               ; Fan out ;
+-------------------------------------------------+---------+
; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[0] ; 2       ;
; Total number of inverted registers = 1          ;         ;
+-------------------------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------+
; 3:1                ; 2 bits    ; 4 LEs         ; 0 LEs                ; 4 LEs                  ; Yes        ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[1]                 ;
; 3:1                ; 2 bits    ; 4 LEs         ; 0 LEs                ; 4 LEs                  ; Yes        ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_RI|iCount[0]                  ;
; 3:1                ; 2 bits    ; 4 LEs         ; 0 LEs                ; 4 LEs                  ; Yes        ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[1]                 ;
; 3:1                ; 2 bits    ; 4 LEs         ; 0 LEs                ; 4 LEs                  ; Yes        ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[1]                 ;
; 3:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |UART16750|uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ;
; 3:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |UART16750|uart_16750:inst|iFECounter[5]                                           ;
; 4:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState~29                      ;
; 10:1               ; 2 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |UART16750|uart_16750:inst|Mux0                                                    ;
; 10:1               ; 4 bits    ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; No         ; |UART16750|uart_16750:inst|Mux5                                                    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                           ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                            ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                           ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                            ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_CTS ;
+----------------+-------+-------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                              ;
+----------------+-------+-------------------------------------------------------------------+
; size           ; 2     ; Signed Integer                                                    ;
+----------------+-------+-------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_DSR ;
+----------------+-------+-------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                              ;
+----------------+-------+-------------------------------------------------------------------+
; size           ; 2     ; Signed Integer                                                    ;
+----------------+-------+-------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_DCD ;
+----------------+-------+-------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                              ;
+----------------+-------+-------------------------------------------------------------------+
; size           ; 2     ; Signed Integer                                                    ;
+----------------+-------+-------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_RI ;
+----------------+-------+------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                             ;
+----------------+-------+------------------------------------------------------------------+
; size           ; 2     ; Signed Integer                                                   ;
+----------------+-------+------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".