📄 uart16750.map.rpt
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+---------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+---------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |UART16750 ; 417 (1) ; 293 (3) ; 1216 ; 0 ; 0 ; 0 ; 36 ; 0 ; |UART16750 ; work ;
; |slib_clock_div:inst2| ; 9 (9) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|slib_clock_div:inst2 ; work ;
; |uart_16750:inst| ; 407 (150) ; 284 (120) ; 1216 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst ; work ;
; |slib_clock_div:UART_BG2| ; 4 (4) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_clock_div:UART_BG2 ; work ;
; |slib_edge_detect:UART_BIDET| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_BIDET ; work ;
; |slib_edge_detect:UART_ED_CTS| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_CTS ; work ;
; |slib_edge_detect:UART_ED_DCD| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_DCD ; work ;
; |slib_edge_detect:UART_ED_DSR| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_DSR ; work ;
; |slib_edge_detect:UART_ED_READ| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_READ ; work ;
; |slib_edge_detect:UART_ED_RI| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_RI ; work ;
; |slib_edge_detect:UART_ED_WRITE| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_WRITE ; work ;
; |slib_edge_detect:UART_FEDET| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_FEDET ; work ;
; |slib_edge_detect:UART_IIC_THRE_ED| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_IIC_THRE_ED ; work ;
; |slib_edge_detect:UART_PEDET| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_PEDET ; work ;
; |slib_edge_detect:UART_RCLK| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_RCLK ; work ;
; |slib_fifo:UART_RXFF| ; 49 (0) ; 29 (0) ; 704 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF ; work ;
; |scfifo:scfifo_component| ; 49 (0) ; 29 (0) ; 704 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component ; work ;
; |scfifo_ko31:auto_generated| ; 49 (0) ; 29 (0) ; 704 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated ; work ;
; |a_dpfifo_7g31:dpfifo| ; 49 (29) ; 29 (12) ; 704 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo ; work ;
; |altsyncram_h981:FIFOram| ; 0 (0) ; 0 (0) ; 704 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram ; work ;
; |cntr_c5b:rd_ptr_msb| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb ; work ;
; |cntr_d5b:wr_ptr| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_d5b:wr_ptr ; work ;
; |cntr_p57:usedw_counter| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter ; work ;
; |slib_fifo:UART_TXFF| ; 50 (0) ; 29 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF ; work ;
; |scfifo:scfifo_component| ; 50 (0) ; 29 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component ; work ;
; |scfifo_an31:auto_generated| ; 50 (0) ; 29 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated ; work ;
; |a_dpfifo_te31:dpfifo| ; 50 (30) ; 29 (12) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo ; work ;
; |altsyncram_t681:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram ; work ;
; |cntr_c5b:rd_ptr_msb| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb ; work ;
; |cntr_d5b:wr_ptr| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr ; work ;
; |cntr_p57:usedw_counter| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter ; work ;
; |slib_input_filter:UART_IF_CTS| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_CTS ; work ;
; |slib_input_filter:UART_IF_DCD| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_DCD ; work ;
; |slib_input_filter:UART_IF_DSR| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_DSR ; work ;
; |slib_input_filter:UART_IF_RI| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_RI ; work ;
; |slib_input_sync:UART_IS_CTS| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_sync:UART_IS_CTS ; work ;
; |slib_input_sync:UART_IS_DCD| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_sync:UART_IS_DCD ; work ;
; |slib_input_sync:UART_IS_DSR| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_sync:UART_IS_DSR ; work ;
; |slib_input_sync:UART_IS_RI| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_sync:UART_IS_RI ; work ;
; |slib_input_sync:UART_IS_SIN| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_sync:UART_IS_SIN ; work ;
; |uart_baudgen:UART_BG16| ; 27 (27) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|uart_baudgen:UART_BG16 ; work ;
; |uart_interrupt:UART_IIC| ; 12 (12) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|uart_interrupt:UART_IIC ; work ;
; |uart_receiver:UART_RX| ; 66 (47) ; 32 (21) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|uart_receiver:UART_RX ; work ;
; |slib_counter:RX_BRC| ; 10 (10) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC ; work ;
; |slib_mv_filter:RX_MVF| ; 9 (9) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF ; work ;
; |uart_transmitter:UART_TX| ; 34 (34) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|uart_transmitter:UART_TX ; work ;
+---------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64 ; 11 ; 64 ; 11 ; 704 ; None ;
; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64 ; 8 ; 64 ; 8 ; 512 ; None ;
+------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
Encoding Type: One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |UART16750|uart_16750:inst|\UART_TXPROC:State ;
+----------------------------+--------------------------+--------------------------+----------------------------+-------------------------+
; Name ; \UART_TXPROC:State.txend ; \UART_TXPROC:State.txrun ; \UART_TXPROC:State.txstart ; \UART_TXPROC:State.idle ;
+----------------------------+--------------------------+--------------------------+----------------------------+-------------------------+
; \UART_TXPROC:State.idle ; 0 ; 0 ; 0 ; 0 ;
; \UART_TXPROC:State.txstart ; 0 ; 0 ; 1 ; 1 ;
; \UART_TXPROC:State.txrun ; 0 ; 1 ; 0 ; 1 ;
; \UART_TXPROC:State.txend ; 1 ; 0 ; 0 ; 1 ;
+----------------------------+--------------------------+--------------------------+----------------------------+-------------------------+
Encoding Type: One-Hot
+---------------------------------------------------------------------------------------------------+
; State Machine - |UART16750|uart_16750:inst|uart_receiver:UART_RX|CState ;
+--------------+--------------+-------------+------------+-------------+--------------+-------------+
; Name ; CState.mwait ; CState.stop ; CState.par ; CState.data ; CState.start ; CState.idle ;
+--------------+--------------+-------------+------------+-------------+--------------+-------------+
; CState.idle ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; CState.start ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
; CState.data ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
; CState.par ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
; CState.stop ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
; CState.mwait ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
+--------------+--------------+-------------+------------+-------------+--------------+-------------+
Encoding Type: One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState ;
+--------------+--------------+-------------+------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+--------------+-------------+
; Name ; CState.stop2 ; CState.stop ; CState.par ; CState.bit7 ; CState.bit6 ; CState.bit5 ; CState.bit4 ; CState.bit3 ; CState.bit2 ; CState.bit1 ; CState.bit0 ; CState.start ; CState.idle ;
+--------------+--------------+-------------+------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+--------------+-------------+
; CState.idle ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; CState.start ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
; CState.bit0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
; CState.bit1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
; CState.bit2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
; CState.bit3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; CState.bit4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
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