📄 uart16750.map.rpt
字号:
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+--------------------------------------------------------------+--------------------+--------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+------------------------------------------+-----------------+------------------------------------+------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+------------------------------------------+-----------------+------------------------------------+------------------------------------------------------------+
; ../../../rtl/vhdl/uart_transmitter.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/uart_transmitter.vhd ;
; ../../../rtl/vhdl/slib_clock_div.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/slib_clock_div.vhd ;
; ../../../rtl/vhdl/slib_counter.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/slib_counter.vhd ;
; ../../../rtl/vhdl/slib_edge_detect.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/slib_edge_detect.vhd ;
; ../../../rtl/vhdl/slib_fifo_cyclone2.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/slib_fifo_cyclone2.vhd ;
; ../../../rtl/vhdl/slib_input_filter.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/slib_input_filter.vhd ;
; ../../../rtl/vhdl/slib_input_sync.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/slib_input_sync.vhd ;
; ../../../rtl/vhdl/slib_mv_filter.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/slib_mv_filter.vhd ;
; ../../../rtl/vhdl/uart_16750.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/uart_16750.vhd ;
; ../../../rtl/vhdl/uart_baudgen.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/uart_baudgen.vhd ;
; ../../../rtl/vhdl/uart_interrupt.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/uart_interrupt.vhd ;
; ../../../rtl/vhdl/uart_receiver.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/uart_receiver.vhd ;
; UART16750.bdf ; yes ; User Block Diagram/Schematic File ; R:/uart16750/syn/Altera/CycloneII/UART16750.bdf ;
; scfifo.tdf ; yes ; Megafunction ; r:/altera/80/quartus/libraries/megafunctions/scfifo.tdf ;
; a_regfifo.inc ; yes ; Megafunction ; r:/altera/80/quartus/libraries/megafunctions/a_regfifo.inc ;
; a_dpfifo.inc ; yes ; Megafunction ; r:/altera/80/quartus/libraries/megafunctions/a_dpfifo.inc ;
; a_i2fifo.inc ; yes ; Megafunction ; r:/altera/80/quartus/libraries/megafunctions/a_i2fifo.inc ;
; a_fffifo.inc ; yes ; Megafunction ; r:/altera/80/quartus/libraries/megafunctions/a_fffifo.inc ;
; a_f2fifo.inc ; yes ; Megafunction ; r:/altera/80/quartus/libraries/megafunctions/a_f2fifo.inc ;
; aglobal80.inc ; yes ; Megafunction ; r:/altera/80/quartus/libraries/megafunctions/aglobal80.inc ;
; db/scfifo_an31.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/scfifo_an31.tdf ;
; db/a_dpfifo_te31.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/a_dpfifo_te31.tdf ;
; db/altsyncram_t681.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/altsyncram_t681.tdf ;
; db/cntr_c5b.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/cntr_c5b.tdf ;
; db/cntr_p57.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/cntr_p57.tdf ;
; db/cntr_d5b.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/cntr_d5b.tdf ;
; db/scfifo_ko31.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/scfifo_ko31.tdf ;
; db/a_dpfifo_7g31.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/a_dpfifo_7g31.tdf ;
; db/altsyncram_h981.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/altsyncram_h981.tdf ;
+------------------------------------------+-----------------+------------------------------------+------------------------------------------------------------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements ; 417 ;
; ; ;
; Total combinational functions ; 417 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 223 ;
; -- 3 input functions ; 72 ;
; -- <=2 input functions ; 122 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 348 ;
; -- arithmetic mode ; 69 ;
; ; ;
; Total registers ; 293 ;
; -- Dedicated logic registers ; 293 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 36 ;
; Total memory bits ; 1216 ;
; Maximum fan-out node ; CLK ;
; Maximum fan-out ; 312 ;
; Total fan-out ; 2682 ;
; Average fan-out ; 3.51 ;
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