uart16750.map.rpt

Implements a 16550/16750 UART core

Analysis & Synthesis report for UART16750
Tue Feb 17 23:02:31 2009
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |UART16750|uart_16750:inst|\UART_TXPROC:State
  9. State Machine - |UART16750|uart_16750:inst|uart_receiver:UART_RX|CState
 10. State Machine - |UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState
 11. General Register Statistics
 12. Inverted Register Statistics
 13. Multiplexer Restructuring Statistics (Restructuring Performed)
 14. Source assignments for uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram
 15. Source assignments for uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram
 16. Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_CTS
 17. Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_DSR
 18. Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_DCD
 19. Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_RI
 20. Parameter Settings for User Entity Instance: uart_16750:inst|slib_clock_div:UART_BG2
 21. Parameter Settings for User Entity Instance: uart_16750:inst|slib_fifo:UART_TXFF
 22. Parameter Settings for User Entity Instance: uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component
 23. Parameter Settings for User Entity Instance: uart_16750:inst|slib_fifo:UART_RXFF
 24. Parameter Settings for User Entity Instance: uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component
 25. Parameter Settings for User Entity Instance: uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC
 26. Parameter Settings for User Entity Instance: uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF
 27. Parameter Settings for User Entity Instance: slib_clock_div:inst2
 28. scfifo Parameter Settings by Entity Instance
 29. Analysis & Synthesis Messages
 30. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Tue Feb 17 23:02:31 2009    ;
; Quartus II Version                 ; 8.0 Build 215 05/29/2008 SJ Full Version ;
; Revision Name                      ; UART16750                                ;
; Top-level Entity Name              ; UART16750                                ;
; Family                             ; Cyclone II                               ;
; Total logic elements               ; 417                                      ;
;     Total combinational functions  ; 417                                      ;
;     Dedicated logic registers      ; 293                                      ;
; Total registers                    ; 293                                      ;
; Total pins                         ; 36                                       ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 1,216                                    ;
; Embedded Multiplier 9-bit elements ; 0                                        ;
; Total PLLs                         ; 0                                        ;
+------------------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                          ;
+--------------------------------------------------------------+--------------------+--------------------+
; Option                                                       ; Setting            ; Default Value      ;
+--------------------------------------------------------------+--------------------+--------------------+
; Device                                                       ; EP2C5F256C6        ;                    ;
; Top-level entity name                                        ; UART16750          ; UART16750          ;
; Family name                                                  ; Cyclone II         ; Stratix II         ;
; Use Generated Physical Constraints File                      ; Off                ;                    ;
; Use smart compilation                                        ; Off                ; Off                ;
; Maximum processors allowed for parallel compilation          ; 1                  ; 1                  ;
; Restructure Multiplexers                                     ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                          ; Off                ; Off                ;
; Preserve fewer node names                                    ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                    ; Off                ; Off                ;
; Verilog Version                                              ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                 ; VHDL93             ; VHDL93             ;
; State Machine Processing                                     ; Auto               ; Auto               ;
; Safe State Machine                                           ; Off                ; Off                ;
; Extract Verilog State Machines                               ; On                 ; On                 ;
; Extract VHDL State Machines                                  ; On                 ; On                 ;
; Ignore Verilog initial constructs                            ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                   ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops               ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                      ; On                 ; On                 ;
; Parallel Synthesis                                           ; Off                ; Off                ;
; DSP Block Balancing                                          ; Auto               ; Auto               ;
; NOT Gate Push-Back                                           ; On                 ; On                 ;
; Power-Up Don't Care                                          ; On                 ; On                 ;