dds.map.qmsg

一个可用的很不错的DDS 频率合成程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 05 22:03:55 2008 " "Info: Processing started: Fri Dec 05 22:03:55 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dds -c dds " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dds -c dds" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds.vhd 10 5 " "Info: Found 10 design units, including 5 entities, in source file dds.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DDS-ART " "Info: Found design unit 1: DDS-ART" {  } { { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 REG1-ART " "Info: Found design unit 2: REG1-ART" {  } { { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 55 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 SUM99-ART " "Info: Found design unit 3: SUM99-ART" {  } { { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 77 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 REG2-ART " "Info: Found design unit 4: REG2-ART" {  } { { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 103 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 ROM-ART " "Info: Found design unit 5: ROM-ART" {  } { { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 125 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 DDS " "Info: Found entity 1: DDS" {  } { { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 REG1 " "Info: Found entity 2: REG1" {  } { { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 50 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 SUM99 " "Info: Found entity 3: SUM99" {  } { { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 70 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 REG2 " "Info: Found entity 4: REG2" {  } { { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 98 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 ROM " "Info: Found entity 5: ROM" {  } { { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 120 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dds " "Info: Elaborating entity \"dds\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SUM99 SUM99:U0 " "Info: Elaborating entity \"SUM99\" for hierarchy \"SUM99:U0\"" {  } { { "dds.vhd" "U0" { Text "c:/altera/70/quartus/dds/dds.vhd" 39 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "TEMP dds.vhd(90) " "Warning (10492): VHDL Process Statement warning at dds.vhd(90): signal \"TEMP\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 90 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "REG1 REG1:U1 " "Info: Elaborating entity \"REG1\" for hierarchy \"REG1:U1\"" {  } { { "dds.vhd" "U1" { Text "c:/altera/70/quartus/dds/dds.vhd" 40 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ROM ROM:U2 " "Info: Elaborating entity \"ROM\" for hierarchy \"ROM:U2\"" {  } { { "dds.vhd" "U2" { Text "c:/altera/70/quartus/dds/dds.vhd" 41 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "REG2 REG2:U3 " "Info: Elaborating entity \"REG2\" for hierarchy \"REG2:U3\"" {  } { { "dds.vhd" "U3" { Text "c:/altera/70/quartus/dds/dds.vhd" 42 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ROM:U2\|OUTP\[8\] data_in GND " "Warning: Reduced register \"ROM:U2\|OUTP\[8\]\" with stuck data_in port to stuck value GND" {  } { { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 129 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "REG2:U3\|Q\[8\] data_in GND " "Warning: Reduced register \"REG2:U3\|Q\[8\]\" with stuck data_in port to stuck value GND" {  } { { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 107 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WOPT_ROM_FUNCTIONALITY_CHANGE_ALTSYNCRAM" "ROM:U2\|WideNor0~1 " "Warning: Created node \"ROM:U2\|WideNor0~1\" as a ROM by generating altsyncram megafunction to implement register logic with M512, M-LAB, M4K, or M9K memory block. Power-up state differs from the original design." {  } { { "dds.vhd" "WideNor0~1" { Text "c:/altera/70/quartus/dds/dds.vhd" 130 -1 0 } }  } 0 0 "Created node \"%1!s!\" as a ROM by generating altsyncram megafunction to implement register logic with M512, M-LAB, M4K, or M9K memory block. Power-up state differs from the original design." 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_ROM_INFERRED" "ROM:U2\|WideNor0~1 1024 1 " "Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=1024, WIDTH_A=1) from the following design logic: \"ROM:U2\|WideNor0~1\"" {  } { { "dds.vhd" "WideNor0~1" { Text "c:/altera/70/quartus/dds/dds.vhd" 130 -1 0 } }  } 0 0 "Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=%2!d!, WIDTH_A=%3!d!) from the following design logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/altsyncram.tdf" 434 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "ROM:U2\|altsyncram:WideNor0_rtl_0 " "Info: Elaborated megafunction instantiation \"ROM:U2\|altsyncram:WideNor0_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_uau.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_uau.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_uau " "Info: Found entity 1: altsyncram_uau" {  } { { "db/altsyncram_uau.tdf" "" { Text "c:/altera/70/quartus/dds/db/altsyncram_uau.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "Q\[8\] GND " "Warning: Pin \"Q\[8\]\" stuck at GND" {  } { { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 10 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "512 " "Info: Implemented 512 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "13 " "Info: Implemented 13 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "489 " "Info: Implemented 489 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "1 " "Info: Implemented 1 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "143 " "Info: Allocated 143 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 05 22:04:20 2008 " "Info: Processing ended: Fri Dec 05 22:04:20 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:25 " "Info: Elapsed time: 00:00:25" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}