dds.tan.rpt

来自「一个可用的很不错的DDS 频率合成程序」· RPT 代码 · 共 233 行 · 第 1/5 页

; N/A                                     ; 114.16 MHz ( period = 8.760 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg9 ; ROM:U2|OUTP[0]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.455 ns                ;
; N/A                                     ; 117.08 MHz ( period = 8.541 ns )                    ; REG1:U1|Q[4]                                                                                   ; ROM:U2|OUTP[6]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.282 ns                ;
; N/A                                     ; 117.58 MHz ( period = 8.505 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg0 ; ROM:U2|OUTP[5]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.199 ns                ;
; N/A                                     ; 117.58 MHz ( period = 8.505 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg1 ; ROM:U2|OUTP[5]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.199 ns                ;
; N/A                                     ; 117.58 MHz ( period = 8.505 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg2 ; ROM:U2|OUTP[5]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.199 ns                ;
; N/A                                     ; 117.58 MHz ( period = 8.505 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg3 ; ROM:U2|OUTP[5]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.199 ns                ;
; N/A                                     ; 117.58 MHz ( period = 8.505 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg4 ; ROM:U2|OUTP[5]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.199 ns                ;
; N/A                                     ; 117.58 MHz ( period = 8.505 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg5 ; ROM:U2|OUTP[5]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.199 ns                ;
; N/A                                     ; 117.58 MHz ( period = 8.505 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg6 ; ROM:U2|OUTP[5]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.199 ns                ;
; N/A                                     ; 117.58 MHz ( period = 8.505 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg7 ; ROM:U2|OUTP[5]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.199 ns                ;
; N/A                                     ; 117.58 MHz ( period = 8.505 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg8 ; ROM:U2|OUTP[5]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.199 ns                ;
; N/A                                     ; 117.58 MHz ( period = 8.505 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg9 ; ROM:U2|OUTP[5]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.199 ns                ;
; N/A                                     ; 117.59 MHz ( period = 8.504 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg0 ; ROM:U2|OUTP[6]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.198 ns                ;
; N/A                                     ; 117.59 MHz ( period = 8.504 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg1 ; ROM:U2|OUTP[6]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.198 ns                ;
; N/A                                     ; 117.59 MHz ( period = 8.504 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg2 ; ROM:U2|OUTP[6]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.198 ns                ;
; N/A                                     ; 117.59 MHz ( period = 8.504 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg3 ; ROM:U2|OUTP[6]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.198 ns                ;
; N/A                                     ; 117.59 MHz ( period = 8.504 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg4 ; ROM:U2|OUTP[6]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.198 ns                ;
; N/A                                     ; 117.59 MHz ( period = 8.504 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg5 ; ROM:U2|OUTP[6]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.198 ns                ;
; N/A                                     ; 117.59 MHz ( period = 8.504 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg6 ; ROM:U2|OUTP[6]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.198 ns                ;
; N/A                                     ; 117.59 MHz ( period = 8.504 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg7 ; ROM:U2|OUTP[6]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.198 ns                ;
; N/A                                     ; 117.59 MHz ( period = 8.504 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg8 ; ROM:U2|OUTP[6]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.198 ns                ;
; N/A                                     ; 117.59 MHz ( period = 8.504 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg9 ; ROM:U2|OUTP[6]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.198 ns                ;
; N/A                                     ; 118.09 MHz ( period = 8.468 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg0 ; ROM:U2|OUTP[3]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.148 ns                ;
; N/A                                     ; 118.09 MHz ( period = 8.468 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg1 ; ROM:U2|OUTP[3]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.148 ns                ;
; N/A                                     ; 118.09 MHz ( period = 8.468 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg2 ; ROM:U2|OUTP[3]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.148 ns                ;
; N/A                                     ; 118.09 MHz ( period = 8.468 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg3 ; ROM:U2|OUTP[3]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.148 ns                ;
; N/A                                     ; 118.09 MHz ( period = 8.468 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg4 ; ROM:U2|OUTP[3]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.148 ns                ;
; N/A                                     ; 118.09 MHz ( period = 8.468 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg5 ; ROM:U2|OUTP[3]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.148 ns                ;
; N/A                                     ; 118.09 MHz ( period = 8.468 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg6 ; ROM:U2|OUTP[3]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.148 ns                ;
; N/A                                     ; 118.09 MHz ( period = 8.468 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg7 ; ROM:U2|OUTP[3]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.148 ns                ;
; N/A                                     ; 118.09 MHz ( period = 8.468 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg8 ; ROM:U2|OUTP[3]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.148 ns                ;
; N/A                                     ; 118.09 MHz ( period = 8.468 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg9 ; ROM:U2|OUTP[3]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.148 ns                ;
; N/A                                     ; 118.12 MHz ( period = 8.466 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg0 ; ROM:U2|OUTP[2]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.146 ns                ;
; N/A                                     ; 118.12 MHz ( period = 8.466 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg1 ; ROM:U2|OUTP[2]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.146 ns                ;
; N/A                                     ; 118.12 MHz ( period = 8.466 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg2 ; ROM:U2|OUTP[2]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.146 ns                ;
; N/A                                     ; 118.12 MHz ( period = 8.466 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg3 ; ROM:U2|OUTP[2]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.146 ns                ;
; N/A                                     ; 118.12 MHz ( period = 8.466 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg4 ; ROM:U2|OUTP[2]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.146 ns                ;
; N/A                                     ; 118.12 MHz ( period = 8.466 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg5 ; ROM:U2|OUTP[2]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.146 ns                ;
; N/A                                     ; 118.12 MHz ( period = 8.466 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg6 ; ROM:U2|OUTP[2]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.146 ns                ;
; N/A                                     ; 118.12 MHz ( period = 8.466 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg7 ; ROM:U2|OUTP[2]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.146 ns                ;
; N/A                                     ; 118.12 MHz ( period = 8.466 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg8 ; ROM:U2|OUTP[2]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.146 ns                ;
; N/A                                     ; 118.12 MHz ( period = 8.466 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg9 ; ROM:U2|OUTP[2]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.146 ns                ;
; N/A                                     ; 118.58 MHz ( period = 8.433 ns )                    ; REG1:U1|Q[5]                                                                                   ; ROM:U2|OUTP[6]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.174 ns                ;
; N/A                                     ; 120.03 MHz ( period = 8.331 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg0 ; ROM:U2|OUTP[4]                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; 8.019 ns                ;
; N/A                                     ; 120.03 MHz ( period = 8.331 ns )                    ; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ram_block1a0~porta_address_reg1 ; ROM: