mux_16_to_1.vhd

CPU代码-VHDL语言

--选1多路器mux_16_to_1

library ieee;
use ieee.std_logic_1164.all;

entity mux_16_to_1 is
port (
	 input0,
	 input1,
	 input2,
	 input3,
	 input4,
	 input5,
	 input6,
	 input7,
	 input8,
	 input9,
	 input10,
	 input11,
	 input12,
	 input13,
	 input14,
	 input15:   in std_logic_vector(15 downto 0);
	 sel:      in std_logic_vector(3 downto 0);
	 out_put:  out std_logic_vector(15 downto 0));
end mux_16_to_1;

architecture behavioral of mux_16_to_1 is
begin
mux: process(sel, input0, input1, input2, input3,input4,input5,input6,input7,input8,input9,input10,input11,
	 input12,input13,input14,input15)   
begin
	case sel is 
		when "0000" => 
			out_put <= input0;
		when "0001" => 
			out_put <= input1;
		when "0010" => 
			out_put <= input2;
		when "0011" => 
			out_put <= input3;
		when "0100" => 
			out_put <= input4;
		when "0101" => 
			out_put <= input5;
		when "0110" => 
			out_put <= input6;
		when "0111" => 
			out_put <= input7;
		when "1000" => 
			out_put <= input8;
		when "1001" => 
			out_put <= input9;
		when "1010" => 
			out_put <= input10;
		when "1011" => 
			out_put <= input11;
		when "1100" => 
			out_put <= input12;
		when "1101" => 
			out_put <= input13;
		when "1110" => 
			out_put <= input14;
		when "1111" => 
			out_put <= input15;
	end case;
end process;
end behavioral;