reg.vhd

CPU代码-VHDL语言

library ieee;
use ieee.std_logic_1164.all;

entity reg is port
	   (reset: 		in	std_logic;
		d_input: 	in	std_logic_vector(15 downto 0);
		clk:		in	std_logic;
		write: 		in	std_logic;--写允许
	    sel: 		in	std_logic;--片选
		q_output: 	out	std_logic_vector(15 downto 0)
	    );
end reg;

architecture a of reg is
begin
	process(reset,clk)
	begin
		if reset = '0' then
			q_output <= x"0000"; 	
		elsif clk'event and clk = '0' then  --时钟下降沿触发
			if sel ='1' and write = '1' then  ---片选与写允许有效
				q_output <= d_input;
			end if;
		end if;
	end process;
end a;