📄 regfile.vhd
字号:
--通用寄存器组regfile （一入两输出）
library ieee;
use ieee.std_logic_1164.all;
entity regfile is
port ( DR: in std_logic_vector(3 downto 0); --目的寄存器号
SR: in std_logic_vector(3 downto 0); --源寄存器号
write: in std_logic; --允许写寄存器信号
change_z: in std_logic; --如果为1，则重新设置z标志
change_c: in std_logic;
reset: in std_logic;
clk: in std_logic;
c_in: in std_logic;
z_in: in std_logic;
d_input: in std_logic_vector(15 downto 0); --写寄存器的数据
output_DR: out std_logic_vector(15 downto 0);
output_SR: out std_logic_vector(15 downto 0);
c_out: out std_logic; ----输出C状态
z_out: out std_logic;
R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15: out std_logic_vector(15 downto 0)
);
end regfile;
architecture struct of regfile is
signal reg00, reg01, reg02,reg03,reg04, reg05, reg06,reg07,reg08, reg09, reg10,reg11,reg12, reg13, reg14,reg15: std_logic_vector(15 downto 0);
signal sel00, sel01, sel02, sel03,sel04, sel05, sel06, sel07,sel08, sel09, sel10, sel11,sel12, sel13, sel14, sel15: std_logic;
component reg is port
(reset: in std_logic;
d_input: in std_logic_vector(15 downto 0);
clk: in std_logic;
write: in std_logic;--写允许
sel: in std_logic;--片选
q_output: out std_logic_vector(15 downto 0)
);
end component;
component decoder_4_to_16 is
port (
sel: in std_logic_vector(3 downto 0);
sel00: out std_logic;
sel01: out std_logic;
sel02: out std_logic;
sel03: out std_logic;
sel04: out std_logic;
sel05: out std_logic;
sel06: out std_logic;
sel07: out std_logic;
sel08: out std_logic;
sel09: out std_logic;
sel10: out std_logic;
sel11: out std_logic;
sel12: out std_logic;
sel13: out std_logic;
sel14: out std_logic;
sel15: out std_logic
);
end component;
component mux_16_to_1 is
port (
input0,
input1,
input2,
input3,
input4,
input5,
input6,
input7,
input8,
input9,
input10,
input11,
input12,
input13,
input14,
input15: in std_logic_vector(15 downto 0);
sel: in std_logic_vector(3 downto 0);
out_put: out std_logic_vector(15 downto 0));
end component;
begin
R0 <= reg00;
R1 <= reg01;
R2 <= reg02;
R3 <= reg03;
R4 <= reg04;
R5 <= reg05;
R6 <= reg06;
R7 <= reg07;
R8 <= reg08;
R9 <= reg09;
R10 <= reg10;
R11 <= reg11;
R12 <= reg12;
R13 <= reg13;
R14 <= reg14;
R15 <= reg15;
z_c_proc: process(reset,clk)
begin
if reset = '0' then
z_out <= '0';
c_out <= '0';
elsif clk'event and clk = '0' then ---下降沿
if change_z = '1' then -----如果为1，则重新设置z标志
z_out <= z_in; ----产生的Z标志送出
end if;
if change_c = '1' then
c_out <= c_in;
end if;
end if;
end process;
Areg00: reg port map( --寄存器R0
reset => reset,
d_input => d_input,
clk => clk,
write => write,
sel => sel00,
q_output => reg00
);
Areg01: reg port map( --寄存器R1
reset => reset,
d_input => d_input,
clk => clk,
write => write,
sel => sel01,
q_output => reg01
);
Areg02: reg port map( --寄存器R2
reset => reset,
d_input => d_input,
clk => clk,
write => write,
sel => sel02,
q_output => reg02
);
Areg03: reg port map( --寄存器R3
reset => reset,
d_input => d_input,
clk => clk,
write => write,
sel => sel03,
q_output => reg03
);
Areg04: reg port map( --寄存器R4
reset => reset,
d_input => d_input,
clk => clk,
write => write,
sel => sel04,
q_output => reg04
);
Areg05: reg port map( --寄存器R5
reset => reset,
d_input => d_input,
clk => clk,
write => write,
sel => sel05,
q_output => reg05
);
Areg06: reg port map( --寄存器R6
reset => reset,
d_input => d_input,
clk => clk,
write => write,
sel => sel06,
q_output => reg06
);
Areg07: reg port map( --寄存器R7
reset => reset,
d_input => d_input,
clk => clk,
write => write,
sel => sel07,
q_output => reg07
);
Areg08: reg port map( --寄存器R8
reset => reset,
d_input => d_input,
clk => clk,
write => write,
sel => sel08,
q_output => reg08
);
Areg09: reg port map( --寄存器R9
reset => reset,
d_input => d_input,
clk => clk,
write => write,
sel => sel09,
q_output => reg09
);
Areg10: reg port map( --寄存器R10
reset => reset,
d_input => d_input,
clk => clk,
write => write,
sel => sel10,
q_output => reg10
);
Areg11: reg port map( --寄存器R11
reset => reset,
d_input => d_input,
clk => clk,
write => write,
sel => sel11,
q_output => reg11
);
Areg12: reg port map( --寄存器R12
reset => reset,
d_input => d_input,
clk => clk,
write => write,
sel => sel12,
q_output => reg12
);
Areg13: reg port map( --寄存器R13
reset => reset,
d_input => d_input,
clk => clk,
write => write,
sel => sel13,
q_output => reg13
);
Areg14: reg port map( --寄存器R14
reset => reset,
d_input => d_input,
clk => clk,
write => write,
sel => sel14,
q_output => reg14
);
Areg15: reg port map( --寄存器R15
reset => reset,
d_input => d_input,
clk => clk,
write => write,
sel => sel15,
q_output => reg15
);
des_decoder: decoder_4_to_16 port map( --4 - 16译码器
sel => DR,
sel00 => sel00,
sel01 => sel01,
sel02 => sel02,
sel03 => sel03,
sel04 => sel04,
sel05 => sel05,
sel06 => sel06,
sel07 => sel07,
sel08 => sel08,
sel09 => sel09,
sel10 => sel10,
sel11 => sel11,
sel12 => sel12,
sel13 => sel13,
sel14 => sel14,
sel15 => sel15
);
muxA: mux_16_to_1 port map( --目的寄存器读出16选1选择器
input0 => reg00,
input1 => reg01,
input2 => reg02,
input3 => reg03,
input4 => reg04,
input5 => reg05,
input6 => reg06,
input7 => reg07,
input8 => reg08,
input9 => reg09,
input10 => reg10,
input11 => reg11,
input12 => reg12,
input13 => reg13,
input14 => reg14,
input15 => reg15,
sel => DR,
out_put => output_DR
);
muxB: mux_16_to_1 port map( --源寄存器读出16选1选择器
input0 => reg00,
input1 => reg01,
input2 => reg02,
input3 => reg03,
input4 => reg04,
input5 => reg05,
input6 => reg06,
input7 => reg07,
input8 => reg08,
input9 => reg09,
input10 => reg10,
input11 => reg11,
input12 => reg12,
input13 => reg13,
input14 => reg14,
input15 => reg15,
sel => SR,
out_put => output_SR
);
end struct;⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -