fcout.fit.eqn

数字频率计 FPGA 用verilog语言编写

H2L5Q = H2L6Q;


--H2L4Q is dividers:inst|ten_divider:inst2|qout[1]~reg0 at LC6_A5
--operation mode is normal

H2L4Q_lut_out = H2L4Q & (!H2L2Q) # !H2L4Q & H2L2Q & (H2L6Q # !H2L8Q);
H2L4Q = DFFEA(H2L4Q_lut_out, H1L9, Reset, , , , );

--H2L3Q is dividers:inst|ten_divider:inst2|qout[1]~90 at LC6_A5
--operation mode is normal

H2L3Q = H2L4Q;


--H2L2Q is dividers:inst|ten_divider:inst2|qout[0]~reg0 at LC1_A11
--operation mode is normal

H2L2Q_lut_out = !H2L2Q;
H2L2Q = DFFEA(H2L2Q_lut_out, H1L9, Reset, , , , );

--H2L1Q is dividers:inst|ten_divider:inst2|qout[0]~91 at LC1_A11
--operation mode is normal

H2L1Q = H2L2Q;


--H2L8Q is dividers:inst|ten_divider:inst2|qout[3]~reg0 at LC7_A5
--operation mode is normal

H2L8Q_lut_out = H2L8Q & (H2L6Q $ H2L4Q # !H2L2Q) # !H2L8Q & H2L6Q & H2L4Q & H2L2Q;
H2L8Q = DFFEA(H2L8Q_lut_out, H1L9, Reset, , , , );

--H2L7Q is dividers:inst|ten_divider:inst2|qout[3]~92 at LC7_A5
--operation mode is normal

H2L7Q = H2L8Q;


--H2L9 is dividers:inst|ten_divider:inst2|reduce_nor~18 at LC8_A5
--operation mode is normal

H2L9 = !H2L6Q & !H2L4Q & H2L2Q & H2L8Q;

--H2L01 is dividers:inst|ten_divider:inst2|reduce_nor~19 at LC8_A5
--operation mode is normal

H2L01 = !H2L6Q & !H2L4Q & H2L2Q & H2L8Q;


--H6L6Q is dividers:inst|ten_divider:inst12|qout[2]~reg0 at LC5_C10
--operation mode is normal

H6L6Q_lut_out = H6L6Q $ (H6L4Q & H6L2Q);
H6L6Q = DFFEA(H6L6Q_lut_out, H5L9, Reset, , , , );

--H6L5Q is dividers:inst|ten_divider:inst12|qout[2]~89 at LC5_C10
--operation mode is normal

H6L5Q = H6L6Q;


--H6L4Q is dividers:inst|ten_divider:inst12|qout[1]~reg0 at LC6_C10
--operation mode is normal

H6L4Q_lut_out = H6L4Q & (!H6L2Q) # !H6L4Q & H6L2Q & (H6L6Q # !H6L8Q);
H6L4Q = DFFEA(H6L4Q_lut_out, H5L9, Reset, , , , );

--H6L3Q is dividers:inst|ten_divider:inst12|qout[1]~90 at LC6_C10
--operation mode is normal

H6L3Q = H6L4Q;


--H6L2Q is dividers:inst|ten_divider:inst12|qout[0]~reg0 at LC1_C4
--operation mode is normal

H6L2Q_lut_out = !H6L2Q;
H6L2Q = DFFEA(H6L2Q_lut_out, H5L9, Reset, , , , );

--H6L1Q is dividers:inst|ten_divider:inst12|qout[0]~91 at LC1_C4
--operation mode is normal

H6L1Q = H6L2Q;


--H6L8Q is dividers:inst|ten_divider:inst12|qout[3]~reg0 at LC7_C10
--operation mode is normal

H6L8Q_lut_out = H6L8Q & (H6L6Q $ H6L4Q # !H6L2Q) # !H6L8Q & H6L6Q & H6L4Q & H6L2Q;
H6L8Q = DFFEA(H6L8Q_lut_out, H5L9, Reset, , , , );

--H6L7Q is dividers:inst|ten_divider:inst12|qout[3]~92 at LC7_C10
--operation mode is normal

H6L7Q = H6L8Q;


--H6L9 is dividers:inst|ten_divider:inst12|reduce_nor~18 at LC8_C10
--operation mode is normal

H6L9 = !H6L6Q & !H6L4Q & H6L2Q & H6L8Q;

--H6L01 is dividers:inst|ten_divider:inst12|reduce_nor~19 at LC8_C10
--operation mode is normal

H6L01 = !H6L6Q & !H6L4Q & H6L2Q & H6L8Q;


--H4L6Q is dividers:inst|ten_divider:inst4|qout[2]~reg0 at LC5_C3
--operation mode is normal

H4L6Q_lut_out = H4L6Q $ (H4L4Q & H4L2Q);
H4L6Q = DFFEA(H4L6Q_lut_out, H3L9, Reset, , , , );

--H4L5Q is dividers:inst|ten_divider:inst4|qout[2]~89 at LC5_C3
--operation mode is normal

H4L5Q = H4L6Q;


--H4L4Q is dividers:inst|ten_divider:inst4|qout[1]~reg0 at LC6_C3
--operation mode is normal

H4L4Q_lut_out = H4L4Q & (!H4L2Q) # !H4L4Q & H4L2Q & (H4L6Q # !H4L8Q);
H4L4Q = DFFEA(H4L4Q_lut_out, H3L9, Reset, , , , );

--H4L3Q is dividers:inst|ten_divider:inst4|qout[1]~90 at LC6_C3
--operation mode is normal

H4L3Q = H4L4Q;


--H4L2Q is dividers:inst|ten_divider:inst4|qout[0]~reg0 at LC1_A8
--operation mode is normal

H4L2Q_lut_out = !H4L2Q;
H4L2Q = DFFEA(H4L2Q_lut_out, H3L9, Reset, , , , );

--H4L1Q is dividers:inst|ten_divider:inst4|qout[0]~91 at LC1_A8
--operation mode is normal

H4L1Q = H4L2Q;


--H4L8Q is dividers:inst|ten_divider:inst4|qout[3]~reg0 at LC7_C3
--operation mode is normal

H4L8Q_lut_out = H4L8Q & (H4L6Q $ H4L4Q # !H4L2Q) # !H4L8Q & H4L6Q & H4L4Q & H4L2Q;
H4L8Q = DFFEA(H4L8Q_lut_out, H3L9, Reset, , , , );

--H4L7Q is dividers:inst|ten_divider:inst4|qout[3]~92 at LC7_C3
--operation mode is normal

H4L7Q = H4L8Q;


--H4L9 is dividers:inst|ten_divider:inst4|reduce_nor~18 at LC8_C3
--operation mode is normal

H4L9 = !H4L6Q & !H4L4Q & H4L2Q & H4L8Q;

--H4L01 is dividers:inst|ten_divider:inst4|reduce_nor~19 at LC8_C3
--operation mode is normal

H4L01 = !H4L6Q & !H4L4Q & H4L2Q & H4L8Q;


--H1L6Q is dividers:inst|ten_divider:inst1|qout[2]~reg0 at LC3_A11
--operation mode is normal

H1L6Q_lut_out = H1L6Q $ (H1L4Q & H1L2Q);
H1L6Q = DFFEA(H1L6Q_lut_out, G1L5, Reset, , , , );

--H1L5Q is dividers:inst|ten_divider:inst1|qout[2]~89 at LC3_A11
--operation mode is normal

H1L5Q = H1L6Q;


--H1L4Q is dividers:inst|ten_divider:inst1|qout[1]~reg0 at LC4_A11
--operation mode is normal

H1L4Q_lut_out = H1L4Q & (!H1L2Q) # !H1L4Q & H1L2Q & (H1L6Q # !H1L8Q);
H1L4Q = DFFEA(H1L4Q_lut_out, G1L5, Reset, , , , );

--H1L3Q is dividers:inst|ten_divider:inst1|qout[1]~90 at LC4_A11
--operation mode is normal

H1L3Q = H1L4Q;


--H1L2Q is dividers:inst|ten_divider:inst1|qout[0]~reg0 at LC5_A11
--operation mode is normal

H1L2Q_lut_out = !H1L2Q;
H1L2Q = DFFEA(H1L2Q_lut_out, G1L5, Reset, , , , );

--H1L1Q is dividers:inst|ten_divider:inst1|qout[0]~91 at LC5_A11
--operation mode is normal

H1L1Q = H1L2Q;


--H1L8Q is dividers:inst|ten_divider:inst1|qout[3]~reg0 at LC6_A11
--operation mode is normal

H1L8Q_lut_out = H1L8Q & (H1L6Q $ H1L4Q # !H1L2Q) # !H1L8Q & H1L6Q & H1L4Q & H1L2Q;
H1L8Q = DFFEA(H1L8Q_lut_out, G1L5, Reset, , , , );

--H1L7Q is dividers:inst|ten_divider:inst1|qout[3]~92 at LC6_A11
--operation mode is normal

H1L7Q = H1L8Q;


--H1L9 is dividers:inst|ten_divider:inst1|reduce_nor~18 at LC2_A11
--operation mode is normal

H1L9 = !H1L6Q & !H1L4Q & H1L2Q & H1L8Q;

--H1L01 is dividers:inst|ten_divider:inst1|reduce_nor~19 at LC2_A11
--operation mode is normal

H1L01 = !H1L6Q & !H1L4Q & H1L2Q & H1L8Q;


--G1L2Q is dividers:inst|div3:inst|qout[0]~reg0 at LC1_B19
--operation mode is normal

G1L2Q_lut_out = !G1L2Q & !G1L4Q;
G1L2Q = DFFEA(G1L2Q_lut_out, clk_12m, Reset, , , , );

--G1L1Q is dividers:inst|div3:inst|qout[0]~41 at LC1_B19
--operation mode is normal

G1L1Q = G1L2Q;


--G1L4Q is dividers:inst|div3:inst|qout[1]~reg0 at LC3_B19
--operation mode is normal

G1L4Q_lut_out = !G1L4Q & G1L2Q;
G1L4Q = DFFEA(G1L4Q_lut_out, clk_12m, Reset, , , , );

--G1L3Q is dividers:inst|div3:inst|qout[1]~42 at LC3_B19
--operation mode is normal

G1L3Q = G1L4Q;


--G1L5 is dividers:inst|div3:inst|reduce_nor~0 at LC2_B19
--operation mode is normal

G1L5 = !G1L2Q & G1L4Q;

--G1L6 is dividers:inst|div3:inst|reduce_nor~7 at LC2_B19
--operation mode is normal

G1L6 = !G1L2Q & G1L4Q;


--D1L33 is counter_24b:inst3|always0~170 at LC2_B18
--operation mode is normal

D1L33 = (D1L43 & D1L62 & D1_qout[11] & D1_qout[8]) & CASCADE(D1L44);

--D1L74 is counter_24b:inst3|always0~187 at LC2_B18
--operation mode is normal

D1L74 = (D1L43 & D1L62 & D1_qout[11] & D1_qout[8]) & CASCADE(D1L44);


--D1L43 is counter_24b:inst3|always0~171 at LC2_B13
--operation mode is normal

D1L43 = (K1_q[3] & K1_q[0] & !K1_q[2] & !K1_q[1]) & CASCADE(D1L64);

--D1L84 is counter_24b:inst3|always0~188 at LC2_B13
--operation mode is normal

D1L84 = (K1_q[3] & K1_q[0] & !K1_q[2] & !K1_q[1]) & CASCADE(D1L64);


--rang_sel is rang_sel at PIN_11
--operation mode is input

rang_sel = INPUT();


--mode_sel is mode_sel at PIN_10
--operation mode is input

mode_sel = INPUT();


--Reset is Reset at PIN_9
--operation mode is input

Reset = INPUT();


--clock_x is clock_x at PIN_5
--operation mode is input

clock_x = INPUT();


--clk_12m is clk_12m at PIN_3
--operation mode is input

clk_12m = INPUT();


--disp[23] is disp[23] at PIN_59
--operation mode is output

disp[23] = OUTPUT(C1_DATA_OUT_TEMP[23]);


--disp[22] is disp[22] at PIN_58
--operation mode is output

disp[22] = OUTPUT(C1_DATA_OUT_TEMP[22]);


--disp[21] is disp[21] at PIN_54
--operation mode is output

disp[21] = OUTPUT(C1_DATA_OUT_TEMP[21]);


--disp[20] is disp[20] at PIN_53
--operation mode is output

disp[20] = OUTPUT(C1_DATA_OUT_TEMP[20]);


--disp[19] is disp[19] at PIN_52
--operation mode is output

disp[19] = OUTPUT(C1_DATA_OUT_TEMP[19]);


--disp[18] is disp[18] at PIN_51
--operation mode is output

disp[18] = OUTPUT(C1_DATA_OUT_TEMP[18]);


--disp[17] is disp[17] at PIN_50
--operation mode is output

disp[17] = OUTPUT(C1_DATA_OUT_TEMP[17]);


--disp[16] is disp[16] at PIN_49
--operation mode is output

disp[16] = OUTPUT(C1_DATA_OUT_TEMP[16]);


--disp[15] is disp[15] at PIN_48
--operation mode is output

disp[15] = OUTPUT(C1_DATA_OUT_TEMP[15]);


--disp[14] is disp[14] at PIN_47
--operation mode is output

disp[14] = OUTPUT(C1_DATA_OUT_TEMP[14]);


--disp[13] is disp[13] at PIN_39
--operation mode is output

disp[13] = OUTPUT(C1_DATA_OUT_TEMP[13]);


--disp[12] is disp[12] at PIN_38
--operation mode is output

disp[12] = OUTPUT(C1_DATA_OUT_TEMP[12]);


--disp[11] is disp[11] at PIN_37
--operation mode is output

disp[11] = OUTPUT(C1_DATA_OUT_TEMP[11]);


--disp[10] is disp[10] at PIN_36
--operation mode is output

disp[10] = OUTPUT(C1_DATA_OUT_TEMP[10]);


--disp[9] is disp[9] at PIN_35
--operation mode is output

disp[9] = OUTPUT(C1_DATA_OUT_TEMP[9]);


--disp[8] is disp[8] at PIN_30
--operation mode is output

disp[8] = OUTPUT(C1_DATA_OUT_TEMP[8]);


--disp[7] is disp[7] at PIN_29
--operation mode is output

disp[7] = OUTPUT(C1_DATA_OUT_TEMP[7]);


--disp[6] is disp[6] at PIN_28
--operation mode is output

disp[6] = OUTPUT(C1_DATA_OUT_TEMP[6]);


--disp[5] is disp[5] at PIN_27
--operation mode is output

disp[5] = OUTPUT(C1_DATA_OUT_TEMP[5]);


--disp[4] is disp[4] at PIN_25
--operation mode is output

disp[4] = OUTPUT(C1_DATA_OUT_TEMP[4]);


--disp[3] is disp[3] at PIN_24
--operation mode is output

disp[3] = OUTPUT(C1_DATA_OUT_TEMP[3]);


--disp[2] is disp[2] at PIN_23
--operation mode is output

disp[2] = OUTPUT(C1_DATA_OUT_TEMP[2]);


--disp[1] is disp[1] at PIN_22
--operation mode is output

disp[1] = OUTPUT(C1_DATA_OUT_TEMP[1]);


--disp[0] is disp[0] at PIN_21
--operation mode is output

disp[0] = OUTPUT(C1_DATA_OUT_TEMP[0]);