fcout.fit.eqn

数字频率计 FPGA 用verilog语言编写

A1L63 = !E1L4 & D1L201 & D1L42 & !D1L52;

--A1L14 is rtl~105 at LC3_B24
--operation mode is normal

A1L14 = !E1L4 & D1L201 & D1L42 & !D1L52;


--D1L5 is counter_24b:inst3|add~358 at LC5_B24
--operation mode is normal

D1L5 = D1_qout[18] & D1_qout[17] & D1_qout[16];

--D1L51 is counter_24b:inst3|add~368 at LC5_B24
--operation mode is normal

D1L51 = D1_qout[18] & D1_qout[17] & D1_qout[16];


--D1L6 is counter_24b:inst3|add~359 at LC7_B24
--operation mode is normal

D1L6 = D1_qout[17] & D1_qout[16];

--D1L61 is counter_24b:inst3|add~369 at LC7_B24
--operation mode is normal

D1L61 = D1_qout[17] & D1_qout[16];


--D1L49 is counter_24b:inst3|qout~1635 at LC2_B20
--operation mode is normal

D1L49 = D1L52 & !E1L4 & D1L201 & D1L42;

--D1L99 is counter_24b:inst3|qout~1677 at LC2_B20
--operation mode is normal

D1L99 = D1L52 & !E1L4 & D1L201 & D1L42;


--A1L73 is rtl~98 at LC6_B21
--operation mode is normal

A1L73 = D1L49 & !D1L72;

--A1L24 is rtl~106 at LC6_B21
--operation mode is normal

A1L24 = D1L49 & !D1L72;


--D1L7 is counter_24b:inst3|add~360 at LC7_B21
--operation mode is normal

D1L7 = D1_qout[14] & D1_qout[13] & D1_qout[12];

--D1L71 is counter_24b:inst3|add~370 at LC7_B21
--operation mode is normal

D1L71 = D1_qout[14] & D1_qout[13] & D1_qout[12];


--D1L8 is counter_24b:inst3|add~361 at LC5_B18
--operation mode is normal

D1L8 = D1_qout[13] & D1_qout[12];

--D1L81 is counter_24b:inst3|add~371 at LC5_B18
--operation mode is normal

D1L81 = D1_qout[13] & D1_qout[12];


--A1L83 is rtl~100 at LC4_B22
--operation mode is normal

A1L83 = D1L72 & D1L49 & !D1L82;

--A1L34 is rtl~107 at LC4_B22
--operation mode is normal

A1L34 = D1L72 & D1L49 & !D1L82;


--D1L9 is counter_24b:inst3|add~362 at LC5_B22
--operation mode is normal

D1L9 = D1_qout[10] & D1_qout[9] & D1_qout[8];

--D1L91 is counter_24b:inst3|add~372 at LC5_B22
--operation mode is normal

D1L91 = D1_qout[10] & D1_qout[9] & D1_qout[8];


--D1L01 is counter_24b:inst3|add~363 at LC6_B22
--operation mode is normal

D1L01 = D1_qout[9] & D1_qout[8];

--D1L02 is counter_24b:inst3|add~373 at LC6_B22
--operation mode is normal

D1L02 = D1_qout[9] & D1_qout[8];


--A1L93 is rtl~102 at LC3_B13
--operation mode is normal

A1L93 = D1L82 & D1L72 & D1L49 & !D1L03;

--A1L44 is rtl~108 at LC3_B13
--operation mode is normal

A1L44 = D1L82 & D1L72 & D1L49 & !D1L03;


--D1L11 is counter_24b:inst3|add~364 at LC7_B12
--operation mode is normal

D1L11 = D1_qout[6] & D1_qout[5] & D1_qout[4];

--D1L12 is counter_24b:inst3|add~374 at LC7_B12
--operation mode is normal

D1L12 = D1_qout[6] & D1_qout[5] & D1_qout[4];


--D1L21 is counter_24b:inst3|add~365 at LC4_B12
--operation mode is normal

D1L21 = D1_qout[5] & D1_qout[4];

--D1L22 is counter_24b:inst3|add~375 at LC4_B12
--operation mode is normal

D1L22 = D1_qout[5] & D1_qout[4];


--D1L59 is counter_24b:inst3|qout~1652 at LC8_B16
--operation mode is normal

D1L59 = D1L39 & D1L29 & !D1L1;

--D1L001 is counter_24b:inst3|qout~1678 at LC8_B16
--operation mode is normal

D1L001 = D1L39 & D1L29 & !D1L1;


--F2_CLK_out is dividers:inst|Half_freq:inst6|CLK_out at LC5_A8
--operation mode is normal

F2_CLK_out_lut_out = !F2_CLK_out;
F2_CLK_out = DFFEA(F2_CLK_out_lut_out, H3L9, , , , , );

--F2L2Q is dividers:inst|Half_freq:inst6|CLK_out~1 at LC5_A8
--operation mode is normal

F2L2Q = F2_CLK_out;


--F41_CLK_out is dividers:inst|Half_freq:inst21|CLK_out at LC2_C6
--operation mode is normal

F41_CLK_out_lut_out = !F41_CLK_out;
F41_CLK_out = DFFEA(F41_CLK_out_lut_out, H7L9, , , , , );

--F41L2Q is dividers:inst|Half_freq:inst21|CLK_out~1 at LC2_C6
--operation mode is normal

F41L2Q = F41_CLK_out;


--F8_CLK_out is dividers:inst|Half_freq:inst13|CLK_out at LC3_C4
--operation mode is normal

F8_CLK_out_lut_out = !F8_CLK_out;
F8_CLK_out = DFFEA(F8_CLK_out_lut_out, H5L9, , , , , );

--F8L2Q is dividers:inst|Half_freq:inst13|CLK_out~1 at LC3_C4
--operation mode is normal

F8L2Q = F8_CLK_out;


--A1L23 is rtl~14 at LC8_B24
--operation mode is normal

A1L23 = K1_q[3] & (K1_q[2] # K1_q[1]) # !D1L49;

--A1L54 is rtl~109 at LC8_B24
--operation mode is normal

A1L54 = K1_q[3] & (K1_q[2] # K1_q[1]) # !D1L49;


--D1L69 is counter_24b:inst3|qout~1653 at LC1_B21
--operation mode is normal

D1L69 = D1L72 & D1L49;

--D1L101 is counter_24b:inst3|qout~1679 at LC1_B21
--operation mode is normal

D1L101 = D1L72 & D1L49;


--A1L33 is rtl~25 at LC8_B21
--operation mode is normal

A1L33 = D1L82 & D1L1 & D1L03 # !D1L69;

--A1L64 is rtl~110 at LC8_B21
--operation mode is normal

A1L64 = D1L82 & D1L1 & D1L03 # !D1L69;


--A1L43 is rtl~36 at LC8_B22
--operation mode is normal

A1L43 = D1L1 & D1L03 # !D1L69 # !D1L82;

--A1L74 is rtl~111 at LC8_B22
--operation mode is normal

A1L74 = D1L1 & D1L03 # !D1L69 # !D1L82;


--A1L53 is rtl~47 at LC4_B13
--operation mode is normal

A1L53 = D1L1 # !D1L03 # !D1L69 # !D1L82;

--A1L84 is rtl~112 at LC4_B13
--operation mode is normal

A1L84 = D1L1 # !D1L03 # !D1L69 # !D1L82;


--D1L13 is counter_24b:inst3|always0~168 at LC1_B18
--operation mode is normal

D1L13 = D1_qout[15] & D1_qout[12] & !D1_qout[14] & !D1_qout[13];

--D1L34 is counter_24b:inst3|always0~183 at LC1_B18
--operation mode is normal

D1L34 = D1_qout[15] & D1_qout[12] & !D1_qout[14] & !D1_qout[13];

--D1L44 is counter_24b:inst3|always0~184 at LC1_B18
--operation mode is normal

D1L44 = D1_qout[15] & D1_qout[12] & !D1_qout[14] & !D1_qout[13];


--D1L23 is counter_24b:inst3|always0~169 at LC1_B13
--operation mode is normal

D1L23 = D1_qout[7] & D1_qout[4] & !D1_qout[6] & !D1_qout[5];

--D1L54 is counter_24b:inst3|always0~185 at LC1_B13
--operation mode is normal

D1L54 = D1_qout[7] & D1_qout[4] & !D1_qout[6] & !D1_qout[5];

--D1L64 is counter_24b:inst3|always0~186 at LC1_B13
--operation mode is normal

D1L64 = D1_qout[7] & D1_qout[4] & !D1_qout[6] & !D1_qout[5];


--H3L6Q is dividers:inst|ten_divider:inst3|qout[2]~reg0 at LC4_A5
--operation mode is normal

H3L6Q_lut_out = H3L6Q $ (H3L4Q & H3L2Q);
H3L6Q = DFFEA(H3L6Q_lut_out, H2L9, Reset, , , , );

--H3L5Q is dividers:inst|ten_divider:inst3|qout[2]~89 at LC4_A5
--operation mode is normal

H3L5Q = H3L6Q;


--H3L4Q is dividers:inst|ten_divider:inst3|qout[1]~reg0 at LC3_A5
--operation mode is normal

H3L4Q_lut_out = H3L4Q & (!H3L2Q) # !H3L4Q & H3L2Q & (H3L6Q # !H3L8Q);
H3L4Q = DFFEA(H3L4Q_lut_out, H2L9, Reset, , , , );

--H3L3Q is dividers:inst|ten_divider:inst3|qout[1]~90 at LC3_A5
--operation mode is normal

H3L3Q = H3L4Q;


--H3L2Q is dividers:inst|ten_divider:inst3|qout[0]~reg0 at LC2_A5
--operation mode is normal

H3L2Q_lut_out = !H3L2Q;
H3L2Q = DFFEA(H3L2Q_lut_out, H2L9, Reset, , , , );

--H3L1Q is dividers:inst|ten_divider:inst3|qout[0]~91 at LC2_A5
--operation mode is normal

H3L1Q = H3L2Q;


--H3L8Q is dividers:inst|ten_divider:inst3|qout[3]~reg0 at LC1_A5
--operation mode is normal

H3L8Q_lut_out = H3L8Q & (H3L6Q $ H3L4Q # !H3L2Q) # !H3L8Q & H3L6Q & H3L4Q & H3L2Q;
H3L8Q = DFFEA(H3L8Q_lut_out, H2L9, Reset, , , , );

--H3L7Q is dividers:inst|ten_divider:inst3|qout[3]~92 at LC1_A5
--operation mode is normal

H3L7Q = H3L8Q;


--H3L9 is dividers:inst|ten_divider:inst3|reduce_nor~18 at LC2_A8
--operation mode is normal

H3L9 = !H3L6Q & !H3L4Q & H3L2Q & H3L8Q;

--H3L01 is dividers:inst|ten_divider:inst3|reduce_nor~19 at LC2_A8
--operation mode is normal

H3L01 = !H3L6Q & !H3L4Q & H3L2Q & H3L8Q;


--H7L6Q is dividers:inst|ten_divider:inst20|qout[2]~reg0 at LC4_C10
--operation mode is normal

H7L6Q_lut_out = H7L6Q $ (H7L4Q & H7L2Q);
H7L6Q = DFFEA(H7L6Q_lut_out, H6L9, Reset, , , , );

--H7L5Q is dividers:inst|ten_divider:inst20|qout[2]~89 at LC4_C10
--operation mode is normal

H7L5Q = H7L6Q;


--H7L4Q is dividers:inst|ten_divider:inst20|qout[1]~reg0 at LC3_C10
--operation mode is normal

H7L4Q_lut_out = H7L4Q & (!H7L2Q) # !H7L4Q & H7L2Q & (H7L6Q # !H7L8Q);
H7L4Q = DFFEA(H7L4Q_lut_out, H6L9, Reset, , , , );

--H7L3Q is dividers:inst|ten_divider:inst20|qout[1]~90 at LC3_C10
--operation mode is normal

H7L3Q = H7L4Q;


--H7L2Q is dividers:inst|ten_divider:inst20|qout[0]~reg0 at LC2_C10
--operation mode is normal

H7L2Q_lut_out = !H7L2Q;
H7L2Q = DFFEA(H7L2Q_lut_out, H6L9, Reset, , , , );

--H7L1Q is dividers:inst|ten_divider:inst20|qout[0]~91 at LC2_C10
--operation mode is normal

H7L1Q = H7L2Q;


--H7L8Q is dividers:inst|ten_divider:inst20|qout[3]~reg0 at LC1_C10
--operation mode is normal

H7L8Q_lut_out = H7L8Q & (H7L6Q $ H7L4Q # !H7L2Q) # !H7L8Q & H7L6Q & H7L4Q & H7L2Q;
H7L8Q = DFFEA(H7L8Q_lut_out, H6L9, Reset, , , , );

--H7L7Q is dividers:inst|ten_divider:inst20|qout[3]~92 at LC1_C10
--operation mode is normal

H7L7Q = H7L8Q;


--H7L9 is dividers:inst|ten_divider:inst20|reduce_nor~18 at LC3_C6
--operation mode is normal

H7L9 = !H7L6Q & !H7L4Q & H7L2Q & H7L8Q;

--H7L01 is dividers:inst|ten_divider:inst20|reduce_nor~19 at LC3_C6
--operation mode is normal

H7L01 = !H7L6Q & !H7L4Q & H7L2Q & H7L8Q;


--H5L6Q is dividers:inst|ten_divider:inst5|qout[2]~reg0 at LC4_C3
--operation mode is normal

H5L6Q_lut_out = H5L6Q $ (H5L4Q & H5L2Q);
H5L6Q = DFFEA(H5L6Q_lut_out, H4L9, Reset, , , , );

--H5L5Q is dividers:inst|ten_divider:inst5|qout[2]~89 at LC4_C3
--operation mode is normal

H5L5Q = H5L6Q;


--H5L4Q is dividers:inst|ten_divider:inst5|qout[1]~reg0 at LC3_C3
--operation mode is normal

H5L4Q_lut_out = H5L4Q & (!H5L2Q) # !H5L4Q & H5L2Q & (H5L6Q # !H5L8Q);
H5L4Q = DFFEA(H5L4Q_lut_out, H4L9, Reset, , , , );

--H5L3Q is dividers:inst|ten_divider:inst5|qout[1]~90 at LC3_C3
--operation mode is normal

H5L3Q = H5L4Q;


--H5L2Q is dividers:inst|ten_divider:inst5|qout[0]~reg0 at LC2_C3
--operation mode is normal

H5L2Q_lut_out = !H5L2Q;
H5L2Q = DFFEA(H5L2Q_lut_out, H4L9, Reset, , , , );

--H5L1Q is dividers:inst|ten_divider:inst5|qout[0]~91 at LC2_C3
--operation mode is normal

H5L1Q = H5L2Q;


--H5L8Q is dividers:inst|ten_divider:inst5|qout[3]~reg0 at LC1_C3
--operation mode is normal

H5L8Q_lut_out = H5L8Q & (H5L6Q $ H5L4Q # !H5L2Q) # !H5L8Q & H5L6Q & H5L4Q & H5L2Q;
H5L8Q = DFFEA(H5L8Q_lut_out, H4L9, Reset, , , , );

--H5L7Q is dividers:inst|ten_divider:inst5|qout[3]~92 at LC1_C3
--operation mode is normal

H5L7Q = H5L8Q;


--H5L9 is dividers:inst|ten_divider:inst5|reduce_nor~18 at LC1_C1
--operation mode is normal

H5L9 = !H5L6Q & !H5L4Q & H5L2Q & H5L8Q;

--H5L01 is dividers:inst|ten_divider:inst5|reduce_nor~19 at LC1_C1
--operation mode is normal

H5L01 = !H5L6Q & !H5L4Q & H5L2Q & H5L8Q;


--H2L6Q is dividers:inst|ten_divider:inst2|qout[2]~reg0 at LC5_A5
--operation mode is normal

H2L6Q_lut_out = H2L6Q $ (H2L4Q & H2L2Q);
H2L6Q = DFFEA(H2L6Q_lut_out, H1L9, Reset, , , , );

--H2L5Q is dividers:inst|ten_divider:inst2|qout[2]~89 at LC5_A5
--operation mode is normal