fcout.tan.qmsg

数字频率计 FPGA 用verilog语言编写

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "50 " "Warning: Found 50 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|div3:inst\|qout\[1\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|div3:inst\|qout\[1\]~reg0\" as buffer" {  } { { "div3.v" "" { Text "D:/fcout/div3.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|div3:inst\|qout\[1\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|div3:inst\|qout\[0\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|div3:inst\|qout\[0\]~reg0\" as buffer" {  } { { "div3.v" "" { Text "D:/fcout/div3.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|div3:inst\|qout\[0\]~reg0" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "dividers:inst\|div3:inst\|reduce_nor~0 " "Info: Detected gated clock \"dividers:inst\|div3:inst\|reduce_nor~0\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|div3:inst\|reduce_nor~0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst1\|qout\[3\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst1\|qout\[3\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst1\|qout\[3\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst1\|qout\[0\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst1\|qout\[0\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst1\|qout\[0\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst1\|qout\[1\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst1\|qout\[1\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst1\|qout\[1\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst1\|qout\[2\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst1\|qout\[2\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst1\|qout\[2\]~reg0" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "dividers:inst\|ten_divider:inst1\|reduce_nor~18 " "Info: Detected gated clock \"dividers:inst\|ten_divider:inst1\|reduce_nor~18\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst1\|reduce_nor~18" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst5\|qout\[3\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst5\|qout\[3\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst5\|qout\[3\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst4\|qout\[3\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst4\|qout\[3\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst4\|qout\[3\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst4\|qout\[0\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst4\|qout\[0\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst4\|qout\[0\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst4\|qout\[1\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst4\|qout\[1\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst4\|qout\[1\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst4\|qout\[2\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst4\|qout\[2\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst4\|qout\[2\]~reg0" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "dividers:inst\|ten_divider:inst4\|reduce_nor~18 " "Info: Detected gated clock \"dividers:inst\|ten_divider:inst4\|reduce_nor~18\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst4\|reduce_nor~18" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst5\|qout\[1\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst5\|qout\[1\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst5\|qout\[1\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst5\|qout\[0\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst5\|qout\[0\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst5\|qout\[0\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst5\|qout\[2\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst5\|qout\[2\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst5\|qout\[2\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst20\|qout\[3\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst20\|qout\[3\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst20\|qout\[3\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst12\|qout\[3\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst12\|qout\[3\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst12\|qout\[3\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst12\|qout\[0\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst12\|qout\[0\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst12\|qout\[0\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst12\|qout\[1\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst12\|qout\[1\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst12\|qout\[1\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst12\|qout\[2\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst12\|qout\[2\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst12\|qout\[2\]~reg0" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "dividers:inst\|ten_divider:inst12\|reduce_nor~18 " "Info: Detected gated clock \"dividers:inst\|ten_divider:inst12\|reduce_nor~18\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst12\|reduce_nor~18" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst20\|qout\[1\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst20\|qout\[1\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst20\|qout\[1\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst20\|qout\[0\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst20\|qout\[0\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst20\|qout\[0\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst20\|qout\[2\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst20\|qout\[2\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst20\|qout\[2\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst3\|qout\[3\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst3\|qout\[3\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst3\|qout\[3\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst2\|qout\[3\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst2\|qout\[3\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst2\|qout\[3\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst2\|qout\[0\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst2\|qout\[0\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst2\|qout\[0\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst2\|qout\[1\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst2\|qout\[1\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst2\|qout\[1\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst2\|qout\[2\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst2\|qout\[2\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst2\|qout\[2\]~reg0" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "dividers:inst\|ten_divider:inst2\|reduce_nor~18 " "Info: Detected gated clock \"dividers:inst\|ten_divider:inst2\|reduce_nor~18\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst2\|reduce_nor~18" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst3\|qout\[1\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst3\|qout\[1\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst3\|qout\[1\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst3\|qout\[0\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst3\|qout\[0\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst3\|qout\[0\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|ten_divider:inst3\|qout\[2\]~reg0 " "Info: Detected ripple clock \"dividers:inst\|ten_divider:inst3\|qout\[2\]~reg0\" as buffer" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst3\|qout\[2\]~reg0" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "dividers:inst\|ten_divider:inst5\|reduce_nor~18 " "Info: Detected gated clock \"dividers:inst\|ten_divider:inst5\|reduce_nor~18\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst5\|reduce_nor~18" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "dividers:inst\|ten_divider:inst20\|reduce_nor~18 " "Info: Detected gated clock \"dividers:inst\|ten_divider:inst20\|reduce_nor~18\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst20\|reduce_nor~18" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "dividers:inst\|ten_divider:inst3\|reduce_nor~18 " "Info: Detected gated clock \"dividers:inst\|ten_divider:inst3\|reduce_nor~18\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|ten_divider:inst3\|reduce_nor~18" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|Half_freq:inst13\|CLK_out " "Info: Detected ripple clock \"dividers:inst\|Half_freq:inst13\|CLK_out\" as buffer" {  } { { "Half_freq.v" "" { Text "D:/fcout/Half_freq.v" 3 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|Half_freq:inst13\|CLK_out" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|Half_freq:inst21\|CLK_out " "Info: Detected ripple clock \"dividers:inst\|Half_freq:inst21\|CLK_out\" as buffer" {  } { { "Half_freq.v" "" { Text "D:/fcout/Half_freq.v" 3 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|Half_freq:inst21\|CLK_out" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|Half_freq:inst6\|CLK_out " "Info: Detected ripple clock \"dividers:inst\|Half_freq:inst6\|CLK_out\" as buffer" {  } { { "Half_freq.v" "" { Text "D:/fcout/Half_freq.v" 3 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|Half_freq:inst6\|CLK_out" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|Half_freq:inst8\|CLK_out " "Info: Detected ripple clock \"dividers:inst\|Half_freq:inst8\|CLK_out\" as buffer" {  } { { "Half_freq.v" "" { Text "D:/fcout/Half_freq.v" 3 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|Half_freq:inst8\|CLK_out" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|Half_freq:inst14\|CLK_out " "Info: Detected ripple clock \"dividers:inst\|Half_freq:inst14\|CLK_out\" as buffer" {  } { { "Half_freq.v" "" { Text "D:/fcout/Half_freq.v" 3 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|Half_freq:inst14\|CLK_out" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|Half_freq:inst15\|CLK_out " "Info: Detected ripple clock \"dividers:inst\|Half_freq:inst15\|CLK_out\" as buffer" {  } { { "Half_freq.v" "" { Text "D:/fcout/Half_freq.v" 3 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|Half_freq:inst15\|CLK_out" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|Half_freq:inst22\|CLK_out " "Info: Detected ripple clock \"dividers:inst\|Half_freq:inst22\|CLK_out\" as buffer" {  } { { "Half_freq.v" "" { Text "D:/fcout/Half_freq.v" 3 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|Half_freq:inst22\|CLK_out" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "dividers:inst\|Half_freq:inst23\|CLK_out " "Info: Detected ripple clock \"dividers:inst\|Half_freq:inst23\|CLK_out\" as buffer" {  } { { "Half_freq.v" "" { Text "D:/fcout/Half_freq.v" 3 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividers:inst\|Half_freq:inst23\|CLK_out" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "mode:inst4\|clock_out2~4 " "Info: Detected gated clock \"mode:inst4\|clock_out2~4\" as buffer" {  } { { "mode.v" "" { Text "D:/fcout/mode.v" 3 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "mode:inst4\|clock_out2~4" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "mode:inst4\|clock_out~86 " "Info: Detected gated clock \"mode:inst4\|clock_out~86\" as buffer" {  } { { "mode.v" "" { Text "D:/fcout/mode.v" 3 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "mode:inst4\|clock_out~86" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "Half_freq:inst5\|CLK_out " "Info: Detected ripple clock \"Half_freq:inst5\|CLK_out\" as buffer" {  } { { "Half_freq.v" "" { Text "D:/fcout/Half_freq.v" 3 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "Half_freq:inst5\|CLK_out" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "mode:inst4\|clock_out~87 " "Info: Detected gated clock \"mode:inst4\|clock_out~87\" as buffer" {  } { { "mode.v" "" { Text "D:/fcout/mode.v" 3 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "mode:inst4\|clock_out~87" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock_x register counter_24b:inst3\|lpm_counter:qout_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] register counter_24b:inst3\|qout\[4\] 29.24 MHz 34.2 ns Internal " "Info: Clock \"clock_x\" has Internal fmax of 29.24 MHz between source register \"counter_24b:inst3\|lpm_counter:qout_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]\" and destination register \"counter_24b:inst3\|qout\[4\]\" (period= 34.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "30.200 ns + Longest register register " "Info: + Longest register to register delay is 30.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter_24b:inst3\|lpm_counter:qout_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 1 REG LC5_B16 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_B16; Fanout = 6; REG Node = 'counter_24b:inst3\|lpm_counter:qout_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "" { counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 4.500 ns counter_24b:inst3\|always0~171 2 COMB LC2_B13 3 " "Info: 2: + IC(2.200 ns) + CELL(2.300 ns) = 4.500 ns; Loc. = LC2_B13; Fanout = 3; COMB Node = 'counter_24b:inst3\|always0~171'" {  } { { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "4.500 ns" { counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[3] counter_24b:inst3|always0~171 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 9.000 ns counter_24b:inst3\|always0~170 3 COMB LC2_B18 2 " "Info: 3: + IC(2.200 ns) + CELL(2.300 ns) = 9.000 ns; Loc. = LC2_B18; Fanout = 2; COMB Node = 'counter_24b:inst3\|always0~170'" {  } { { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "4.500 ns" { counter_24b:inst3|always0~171 counter_24b:inst3|always0~170 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 13.500 ns counter_24b:inst3\|reduce_nor~55 4 COMB LC5_B20 2 " "Info: 4: + IC(2.200 ns) + CELL(2.300 ns) = 13.500 ns; Loc. = LC5_B20; Fanout = 2; COMB Node = 'counter_24b:inst3\|reduce_nor~55'" {  } { { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "4.500 ns" { counter_24b:inst3|always0~170 counter_24b:inst3|reduce_nor~55 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 16.400 ns counter_24b:inst3\|reduce_nor~0 5 COMB LC6_B20 4 " "Info: 5: + IC(0.600 ns) + CELL(2.300 ns) = 16.400 ns; Loc. = LC6_B20; Fanout = 4; COMB Node = 'counter_24b:inst3\|reduce_nor~0'" {  } { { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "2.900 ns" { counter_24b:inst3|reduce_nor~55 counter_24b:inst3|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 19.300 ns counter_24b:inst3\|qout~1635 6 COMB LC2_B20 6 " "Info: 6: + IC(0.600 ns) + CELL(2.300 ns) = 19.300 ns; Loc. = LC2_B20; Fanout = 6; COMB Node = 'counter_24b:inst3\|qout~1635'" {  } { { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "2.900 ns" { counter_24b:inst3|reduce_nor~0 counter_24b:inst3|qout~1635 } "NODE_NAME" } "" } } { "counter_24b.v" "" { Text "D:/fcout/counter_24b.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(1.800 ns) 23.700 ns counter_24b:inst3\|qout~1653 7 COMB LC1_B21 3 " "Info: 7: + IC(2.600 ns) + CELL(1.800 ns) = 23.700 ns; Loc. = LC1_B21; Fanout = 3; COMB Node = 'counter_24b:inst3\|qout~1653'" {  } { { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "4.400 ns" { counter_24b:inst3|qout~1635 counter_24b:inst3|qout~1653 } "NODE_NAME" } "" } } { "counter_24b.v" "" { Text "D:/fcout/counter_24b.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(2.300 ns) 28.400 ns rtl~47 8 COMB LC4_B13 4 " "Info: 8: + IC(2.400 ns) + CELL(2.300 ns) = 28.400 ns; Loc. = LC4_B13; Fanout = 4; COMB Node = 'rtl~47'" {  } { { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "4.700 ns" { counter_24b:inst3|qout~1653 rtl~47 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 30.200 ns counter_24b:inst3\|qout\[4\] 9 REG LC7_B13 6 " "Info: 9: + IC(0.600 ns) + CELL(1.200 ns) = 30.200 ns; Loc. = LC7_B13; Fanout = 6; REG Node = 'counter_24b:inst3\|qout\[4\]'" {  } { { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "1.800 ns" { rtl~47 counter_24b:inst3|qout[4] } "NODE_NAME" } "" } } { "counter_24b.v" "" { Text "D:/fcout/counter_24b.v" 2 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.800 ns 55.63 % " "Info: Total cell delay = 16.800 ns ( 55.63 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.400 ns 44.37 % " "Info: Total interconnect delay = 13.400 ns ( 44.37 % )" {  } {  } 0}  } { { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "30.200 ns" { counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[3] counter_24b:inst3|always0~171 counter_24b:inst3|always0~170 counter_24b:inst3|reduce_nor~55 counter_24b:inst3|reduce_nor~0 counter_24b:inst3|qout~1635 counter_24b:inst3|qout~1653 rtl~47 counter_24b:inst3|qout[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "30.200 ns" { counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[3] counter_24b:inst3|always0~171 counter_24b:inst3|always0~170 counter_24b:inst3|reduce_nor~55 counter_24b:inst3|reduce_nor~0 counter_24b:inst3|qout~1635 counter_24b:inst3|qout~1653 rtl~47 counter_24b:inst3|qout[4] } { 0.000ns 2.200ns 2.200ns 2.200ns 0.600ns 0.600ns 2.600ns 2.400ns 0.600ns } { 0.000ns 2.300ns 2.300ns 2.300ns 2.300ns 2.300ns 1.800ns 2.300ns 1.200ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.400 ns - Smallest " "Info: - Smallest clock skew is -0.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_x destination 13.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clock_x\" to destination register is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clock_x 1 CLK PIN_5 2 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_5; Fanout = 2; CLK Node = 'clock_x'" {  } { { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "" { clock_x } "NODE_NAME" } "" } } { "fcout.bdf" "" { Schematic "D:/fcout/fcout.bdf" { { 128 144 312 144 "clock_x" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(2.300 ns) 9.000 ns mode:inst4\|clock_out2~4 2 COMB LC4_A8 27 " "Info: 2: + IC(3.200 ns) + CELL(2.300 ns) = 9.000 ns; Loc. = LC4_A8; Fanout = 27; COMB Node = 'mode:inst4\|clock_out2~4'" {  } { { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "5.500 ns" { clock_x mode:inst4|clock_out2~4 } "NODE_NAME" } "" } } { "mode.v" "" { Text "D:/fcout/mode.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(0.000 ns) 13.000 ns counter_24b:inst3\|qout\[4\] 3 REG LC7_B13 6 " "Info: 3: + IC(4.000 ns) + CELL(0.000 ns) = 13.000 ns; Loc. = LC7_B13; Fanout = 6; REG Node = 'counter_24b:inst3\|qout\[4\]'" {  } { { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "4.000 ns" { mode:inst4|clock_out2~4 counter_24b:inst3|qout[4] } "NODE_NAME" } "" } } { "counter_24b.v" "" { Text "D:/fcout/counter_24b.v" 2 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.800 ns 44.62 % " "Info: Total cell delay = 5.800 ns ( 44.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.200 ns 55.38 % " "Info: Total interconnect delay = 7.200 ns ( 55.38 % )" {  } {  } 0}  } { { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "13.000 ns" { clock_x mode:inst4|clock_out2~4 counter_24b:inst3|qout[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "13.000 ns" { clock_x clock_x~out mode:inst4|clock_out2~4 counter_24b:inst3|qout[4] } { 0.000ns 0.000ns 3.200ns 4.000ns } { 0.000ns 3.500ns 2.300ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_x source 13.400 ns - Longest register " "Info: - Longest clock path from clock \"clock_x\" to source register is 13.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clock_x 1 CLK PIN_5 2 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_5; Fanout = 2; CLK Node = 'clock_x'" {  } { { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "" { clock_x } "NODE_NAME" } "" } } { "fcout.bdf" "" { Schematic "D:/fcout/fcout.bdf" { { 128 144 312 144 "clock_x" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(2.300 ns) 9.000 ns mode:inst4\|clock_out2~4 2 COMB LC4_A8 27 " "Info: 2: + IC(3.200 ns) + CELL(2.300 ns) = 9.000 ns; Loc. = LC4_A8; Fanout = 27; COMB Node = 'mode:inst4\|clock_out2~4'" {  } { { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "5.500 ns" { clock_x mode:inst4|clock_out2~4 } "NODE_NAME" } "" } } { "mode.v" "" { Text "D:/fcout/mode.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.400 ns) + CELL(0.000 ns) 13.400 ns counter_24b:inst3\|lpm_counter:qout_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 3 REG LC5_B16 6 " "Info: 3: + IC(4.400 ns) + CELL(0.000 ns) = 13.400 ns; Loc. = LC5_B16; Fanout = 6; REG Node = 'counter_24b:inst3\|lpm_counter:qout_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "4.400 ns" { mode:inst4|clock_out2~4 counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.800 ns 43.28 % " "Info: Total cell delay = 5.800 ns ( 43.28 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.600 ns 56.72 % " "Info: Total interconnect delay = 7.600 ns ( 56.72 % )" {  } {  } 0}  } { { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "13.400 ns" { clock_x mode:inst4|clock_out2~4 counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "13.400 ns" { clock_x clock_x~out mode:inst4|clock_out2~4 counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 3.200ns 4.400ns } { 0.000ns 3.500ns 2.300ns 0.000ns } } }  } 0}  } { { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "13.000 ns" { clock_x mode:inst4|clock_out2~4 counter_24b:inst3|qout[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "13.000 ns" { clock_x clock_x~out mode:inst4|clock_out2~4 counter_24b:inst3|qout[4] } { 0.000ns 0.000ns 3.200ns 4.000ns } { 0.000ns 3.500ns 2.300ns 0.000ns } } } { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "13.400 ns" { clock_x mode:inst4|clock_out2~4 counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "13.400 ns" { clock_x clock_x~out mode:inst4|clock_out2~4 counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 3.200ns 4.400ns } { 0.000ns 3.500ns 2.300ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "counter_24b.v" "" { Text "D:/fcout/counter_24b.v" 2 -1 0 } }  } 0}  } { { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "30.200 ns" { counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[3] counter_24b:inst3|always0~171 counter_24b:inst3|always0~170 counter_24b:inst3|reduce_nor~55 counter_24b:inst3|reduce_nor~0 counter_24b:inst3|qout~1635 counter_24b:inst3|qout~1653 rtl~47 counter_24b:inst3|qout[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "30.200 ns" { counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[3] counter_24b:inst3|always0~171 counter_24b:inst3|always0~170 counter_24b:inst3|reduce_nor~55 counter_24b:inst3|reduce_nor~0 counter_24b:inst3|qout~1635 counter_24b:inst3|qout~1653 rtl~47 counter_24b:inst3|qout[4] } { 0.000ns 2.200ns 2.200ns 2.200ns 0.600ns 0.600ns 2.600ns 2.400ns 0.600ns } { 0.000ns 2.300ns 2.300ns 2.300ns 2.300ns 2.300ns 1.800ns 2.300ns 1.200ns } } } { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "13.000 ns" { clock_x mode:inst4|clock_out2~4 counter_24b:inst3|qout[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "13.000 ns" { clock_x clock_x~out mode:inst4|clock_out2~4 counter_24b:inst3|qout[4] } { 0.000ns 0.000ns 3.200ns 4.000ns } { 0.000ns 3.500ns 2.300ns 0.000ns } } } { "D:/fcout/db/fcout_cmp.qrpt" "" { Report "D:/fcout/db/fcout_cmp.qrpt" Compiler "fcout" "UNKNOWN" "V1" "D:/fcout/db/fcout.quartus_db" { Floorplan "D:/fcout/" "" "13.400 ns" { clock_x mode:inst4|clock_out2~4 counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "13.400 ns" { clock_x clock_x~out mode:inst4|clock_out2~4 counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 3.200ns 4.400ns } { 0.000ns 3.500ns 2.300ns 0.000ns } } }  } 0}