fcout.tan.qmsg

数字频率计 FPGA 用verilog语言编写

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock_x " "Info: Assuming node \"clock_x\" is an undefined clock" {  } { { "fcout.bdf" "" { Schematic "D:/fcout/fcout.bdf" { { 128 144 312 144 "clock_x" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clock_x" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_12m " "Info: Assuming node \"clk_12m\" is an undefined clock" {  } { { "fcout.bdf" "" { Schematic "D:/fcout/fcout.bdf" { { 320 -24 144 336 "clk_12m" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_12m" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "rang_sel " "Info: Assuming node \"rang_sel\" is an undefined clock" {  } { { "fcout.bdf" "" { Schematic "D:/fcout/fcout.bdf" { { 520 264 432 536 "rang_sel" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rang_sel" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "mode_sel " "Info: Assuming node \"mode_sel\" is an undefined clock" {  } { { "fcout.bdf" "" { Schematic "D:/fcout/fcout.bdf" { { 216 560 728 232 "mode_sel" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "mode_sel" } } } }  } 0}  } {  } 0}