fcout.tan.rpt

数字频率计 FPGA 用verilog语言编写

; Worst-case th                ; N/A                                      ; None          ; 29.800 ns                        ; mode_sel                                                                     ; counter_24b:inst3|qout[20]     ;            ; clk_12m  ; 0            ;
; Clock Setup: 'clk_12m'       ; N/A                                      ; None          ; 19.19 MHz ( period = 52.100 ns ) ; dividers:inst|Half_freq:inst23|CLK_out                                       ; counter_24b:inst3|qout[7]      ; clk_12m    ; clk_12m  ; 0            ;
; Clock Setup: 'mode_sel'      ; N/A                                      ; None          ; 29.24 MHz ( period = 34.200 ns ) ; counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; counter_24b:inst3|qout[7]      ; mode_sel   ; mode_sel ; 0            ;
; Clock Setup: 'clock_x'       ; N/A                                      ; None          ; 29.24 MHz ( period = 34.200 ns ) ; counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; counter_24b:inst3|qout[7]      ; clock_x    ; clock_x  ; 0            ;
; Clock Hold: 'clk_12m'        ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; display:inst2|DATA_OUT_TEMP[0] ; clk_12m    ; clk_12m  ; 115          ;
; Clock Hold: 'clock_x'        ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; display:inst2|DATA_OUT_TEMP[0] ; clock_x    ; clock_x  ; 19           ;
; Total number of failed paths ;                                          ;               ;                                  ;                                                                              ;                                ;            ;          ; 134          ;
+------------------------------+------------------------------------------+---------------+----------------------------------+------------------------------------------------------------------------------+--------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPF10K10LC84-4     ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock_x         ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; clk_12m         ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; rang_sel        ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; mode_sel        ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock_x'                                                                                                                                                                                                                                                                                                                                                  ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------+------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+