ten_divider.v

数字频率计 FPGA 用verilog语言编写

module ten_divider(qout,cout,reset,clk);
output[3:0] qout;
output cout;
input clk,reset;
reg[3:0] qout;
assign    cout=(qout==4'h9)?1'b1:1'b0;  //产生进位输出信号
 
always @(posedge clk or negedge reset) //clk 上升沿时刻计数
	begin
		if (!reset) qout<=4'h0; //同步复位
		else
		  begin
		      if(qout==9) begin qout<=0;end
		
		      else   begin  qout=qout+1; end	
		  end
	end
endmodule