fcout.map.eqn

数字频率计 FPGA 用verilog语言编写

K1_q[2]_lut_out = (K1_q[2] $ K1L5) & D1L59;
K1_q[2] = DFFEA(K1_q[2]_lut_out, E1L1, Reset, , , , );

--K1L51Q is counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[2]~1
--operation mode is clrb_cntr

K1L51Q = K1_q[2];

--K1L7 is counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

K1L7 = CARRY(K1_q[2] & (K1L5));


--K1_q[1] is counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

K1_q[1]_lut_out = (K1_q[1] $ K1L3) & D1L59;
K1_q[1] = DFFEA(K1_q[1]_lut_out, E1L1, Reset, , , , );

--K1L31Q is counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[1]~2
--operation mode is clrb_cntr

K1L31Q = K1_q[1];

--K1L5 is counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

K1L5 = CARRY(K1_q[1] & (K1L3));


--K1_q[0] is counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

K1_q[0]_lut_out = (!K1_q[0]) & D1L59;
K1_q[0] = DFFEA(K1_q[0]_lut_out, E1L1, Reset, , , , );

--K1L11Q is counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[0]~3
--operation mode is clrb_cntr

K1L11Q = K1_q[0];

--K1L3 is counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

K1L3 = CARRY(K1_q[0]);


--D1L32 is counter_24b:inst3|always0~153
--operation mode is normal

D1L32 = !D1_qout[18] & !D1_qout[17];

--D1L53 is counter_24b:inst3|always0~175
--operation mode is normal

D1L53 = !D1_qout[18] & !D1_qout[17];


--D1L301 is counter_24b:inst3|reduce_nor~55
--operation mode is normal

D1L301 = D1L33 & D1L32 & D1_qout[19] & D1_qout[16];

--D1L601 is counter_24b:inst3|reduce_nor~59
--operation mode is normal

D1L601 = D1L33 & D1L32 & D1_qout[19] & D1_qout[16];


--D1L401 is counter_24b:inst3|reduce_nor~56
--operation mode is normal

D1L401 = !D1_qout[22] & !D1_qout[21];

--D1L701 is counter_24b:inst3|reduce_nor~60
--operation mode is normal

D1L701 = !D1_qout[22] & !D1_qout[21];


--D1L201 is counter_24b:inst3|reduce_nor~0
--operation mode is normal

D1L201 = !D1_qout[20] # !D1_qout[23] # !D1L401 # !D1L301;

--D1L801 is counter_24b:inst3|reduce_nor~61
--operation mode is normal

D1L801 = !D1_qout[20] # !D1_qout[23] # !D1L401 # !D1L301;


--D1L42 is counter_24b:inst3|always0~154
--operation mode is normal

D1L42 = D1_qout[23] & (D1_qout[22] # D1_qout[21]) # !D1L301;

--D1L63 is counter_24b:inst3|always0~176
--operation mode is normal

D1L63 = D1_qout[23] & (D1_qout[22] # D1_qout[21]) # !D1L301;


--D1L58 is counter_24b:inst3|qout[21]~1623
--operation mode is normal

D1L58 = D1L201 & !E1L4 & (!D1L42);

--D1L78 is counter_24b:inst3|qout[21]~1674
--operation mode is normal

D1L78 = D1L201 & !E1L4 & (!D1L42);


--D1L3 is counter_24b:inst3|add~356
--operation mode is normal

D1L3 = D1_qout[22] & D1_qout[21] & D1_qout[20];

--D1L31 is counter_24b:inst3|add~366
--operation mode is normal

D1L31 = D1_qout[22] & D1_qout[21] & D1_qout[20];


--D1L1 is counter_24b:inst3|LessThan~147
--operation mode is normal

D1L1 = K1_q[3] & (K1_q[2] # K1_q[1]);

--D1L2 is counter_24b:inst3|LessThan~148
--operation mode is normal

D1L2 = K1_q[3] & (K1_q[2] # K1_q[1]);


--D1L52 is counter_24b:inst3|always0~155
--operation mode is normal

D1L52 = D1_qout[19] & (D1_qout[18] # D1_qout[17]) # !D1L33;

--D1L73 is counter_24b:inst3|always0~177
--operation mode is normal

D1L73 = D1_qout[19] & (D1_qout[18] # D1_qout[17]) # !D1L33;


--D1L62 is counter_24b:inst3|always0~157
--operation mode is normal

D1L62 = !D1_qout[10] & !D1_qout[9];

--D1L83 is counter_24b:inst3|always0~178
--operation mode is normal

D1L83 = !D1_qout[10] & !D1_qout[9];


--D1L501 is counter_24b:inst3|reduce_nor~57
--operation mode is normal

D1L501 = D1L43 & D1L62 & D1_qout[11] & D1_qout[8];

--D1L901 is counter_24b:inst3|reduce_nor~62
--operation mode is normal

D1L901 = D1L43 & D1L62 & D1_qout[11] & D1_qout[8];


--D1L72 is counter_24b:inst3|always0~158
--operation mode is normal

D1L72 = D1_qout[15] & (D1_qout[14] # D1_qout[13]) # !D1L501;

--D1L93 is counter_24b:inst3|always0~179
--operation mode is normal

D1L93 = D1_qout[15] & (D1_qout[14] # D1_qout[13]) # !D1L501;


--D1L82 is counter_24b:inst3|always0~159
--operation mode is normal

D1L82 = D1_qout[11] & (D1_qout[10] # D1_qout[9]) # !D1L43;

--D1L04 is counter_24b:inst3|always0~180
--operation mode is normal

D1L04 = D1_qout[11] & (D1_qout[10] # D1_qout[9]) # !D1L43;


--D1L92 is counter_24b:inst3|always0~160
--operation mode is normal

D1L92 = K1_q[3] & K1_q[0] & !K1_q[2] & !K1_q[1];

--D1L14 is counter_24b:inst3|always0~181
--operation mode is normal

D1L14 = K1_q[3] & K1_q[0] & !K1_q[2] & !K1_q[1];


--D1L03 is counter_24b:inst3|always0~161
--operation mode is normal

D1L03 = D1_qout[7] & (D1_qout[6] # D1_qout[5]) # !D1L92;

--D1L24 is counter_24b:inst3|always0~182
--operation mode is normal

D1L24 = D1_qout[7] & (D1_qout[6] # D1_qout[5]) # !D1L92;


--D1L29 is counter_24b:inst3|qout~1624
--operation mode is normal

D1L29 = D1L52 & D1L72 & D1L82 & D1L03;

--D1L79 is counter_24b:inst3|qout~1675
--operation mode is normal

D1L79 = D1L52 & D1L72 & D1L82 & D1L03;


--D1L39 is counter_24b:inst3|qout~1625
--operation mode is normal

D1L39 = !E1L4 & D1L201 & D1L42;

--D1L89 is counter_24b:inst3|qout~1676
--operation mode is normal

D1L89 = !E1L4 & D1L201 & D1L42;


--A1L13 is rtl~3
--operation mode is normal

A1L13 = D1L1 & D1L29 # !D1L39;

--A1L04 is rtl~104
--operation mode is normal

A1L04 = D1L1 & D1L29 # !D1L39;


--F4_CLK_out is dividers:inst|Half_freq:inst8|CLK_out
--operation mode is normal

F4_CLK_out_lut_out = !F4_CLK_out;
F4_CLK_out = DFFEA(F4_CLK_out_lut_out, F2_CLK_out, , , , , );

--F4L2Q is dividers:inst|Half_freq:inst8|CLK_out~1
--operation mode is normal

F4L2Q = F4_CLK_out;


--E1L1 is mode:inst4|clock_out2~4
--operation mode is normal

E1L1 = mode_sel & F4_CLK_out # !mode_sel & (clock_x);

--E1L2 is mode:inst4|clock_out2~5
--operation mode is normal

E1L2 = mode_sel & F4_CLK_out # !mode_sel & (clock_x);


--F51_CLK_out is dividers:inst|Half_freq:inst22|CLK_out
--operation mode is normal

F51_CLK_out_lut_out = !F51_CLK_out;
F51_CLK_out = DFFEA(F51_CLK_out_lut_out, F41_CLK_out, , , , , );

--F51L2Q is dividers:inst|Half_freq:inst22|CLK_out~1
--operation mode is normal

F51L2Q = F51_CLK_out;


--F9_CLK_out is dividers:inst|Half_freq:inst14|CLK_out
--operation mode is normal

F9_CLK_out_lut_out = !F9_CLK_out;
F9_CLK_out = DFFEA(F9_CLK_out_lut_out, F8_CLK_out, , , , , );

--F9L2Q is dividers:inst|Half_freq:inst14|CLK_out~1
--operation mode is normal

F9L2Q = F9_CLK_out;


--D1L4 is counter_24b:inst3|add~357
--operation mode is normal

D1L4 = D1_qout[21] & D1_qout[20];

--D1L41 is counter_24b:inst3|add~367
--operation mode is normal

D1L41 = D1_qout[21] & D1_qout[20];


--A1L63 is rtl~96
--operation mode is normal

A1L63 = !E1L4 & D1L201 & D1L42 & !D1L52;

--A1L14 is rtl~105
--operation mode is normal

A1L14 = !E1L4 & D1L201 & D1L42 & !D1L52;


--D1L5 is counter_24b:inst3|add~358
--operation mode is normal

D1L5 = D1_qout[18] & D1_qout[17] & D1_qout[16];

--D1L51 is counter_24b:inst3|add~368
--operation mode is normal

D1L51 = D1_qout[18] & D1_qout[17] & D1_qout[16];


--D1L6 is counter_24b:inst3|add~359
--operation mode is normal

D1L6 = D1_qout[17] & D1_qout[16];

--D1L61 is counter_24b:inst3|add~369
--operation mode is normal

D1L61 = D1_qout[17] & D1_qout[16];


--D1L49 is counter_24b:inst3|qout~1635
--operation mode is normal

D1L49 = D1L52 & !E1L4 & D1L201 & D1L42;

--D1L99 is counter_24b:inst3|qout~1677
--operation mode is normal

D1L99 = D1L52 & !E1L4 & D1L201 & D1L42;


--A1L73 is rtl~98
--operation mode is normal

A1L73 = D1L49 & (!D1L72);

--A1L24 is rtl~106
--operation mode is normal

A1L24 = D1L49 & (!D1L72);


--D1L7 is counter_24b:inst3|add~360
--operation mode is normal

D1L7 = D1_qout[14] & D1_qout[13] & D1_qout[12];

--D1L71 is counter_24b:inst3|add~370
--operation mode is normal

D1L71 = D1_qout[14] & D1_qout[13] & D1_qout[12];


--D1L8 is counter_24b:inst3|add~361
--operation mode is normal

D1L8 = D1_qout[13] & D1_qout[12];

--D1L81 is counter_24b:inst3|add~371
--operation mode is normal

D1L81 = D1_qout[13] & D1_qout[12];


--A1L83 is rtl~100
--operation mode is normal

A1L83 = D1L72 & D1L49 & (!D1L82);

--A1L34 is rtl~107
--operation mode is normal

A1L34 = D1L72 & D1L49 & (!D1L82);


--D1L9 is counter_24b:inst3|add~362
--operation mode is normal

D1L9 = D1_qout[10] & D1_qout[9] & D1_qout[8];

--D1L91 is counter_24b:inst3|add~372
--operation mode is normal

D1L91 = D1_qout[10] & D1_qout[9] & D1_qout[8];


--D1L01 is counter_24b:inst3|add~363
--operation mode is normal

D1L01 = D1_qout[9] & D1_qout[8];

--D1L02 is counter_24b:inst3|add~373
--operation mode is normal

D1L02 = D1_qout[9] & D1_qout[8];


--A1L93 is rtl~102
--operation mode is normal

A1L93 = D1L82 & D1L72 & D1L49 & !D1L03;

--A1L44 is rtl~108
--operation mode is normal

A1L44 = D1L82 & D1L72 & D1L49 & !D1L03;


--D1L11 is counter_24b:inst3|add~364
--operation mode is normal

D1L11 = D1_qout[6] & D1_qout[5] & D1_qout[4];

--D1L12 is counter_24b:inst3|add~374
--operation mode is normal

D1L12 = D1_qout[6] & D1_qout[5] & D1_qout[4];


--D1L21 is counter_24b:inst3|add~365
--operation mode is normal

D1L21 = D1_qout[5] & D1_qout[4];

--D1L22 is counter_24b:inst3|add~375
--operation mode is normal

D1L22 = D1_qout[5] & D1_qout[4];


--D1L59 is counter_24b:inst3|qout~1652
--operation mode is normal

D1L59 = D1L39 & D1L29 & (!D1L1);

--D1L001 is counter_24b:inst3|qout~1678
--operation mode is normal

D1L001 = D1L39 & D1L29 & (!D1L1);


--F2_CLK_out is dividers:inst|Half_freq:inst6|CLK_out
--operation mode is normal

F2_CLK_out_lut_out = !F2_CLK_out;
F2_CLK_out = DFFEA(F2_CLK_out_lut_out, H3L9, , , , , );

--F2L2Q is dividers:inst|Half_freq:inst6|CLK_out~1
--operation mode is normal

F2L2Q = F2_CLK_out;


--F41_CLK_out is dividers:inst|Half_freq:inst21|CLK_out
--operation mode is normal

F41_CLK_out_lut_out = !F41_CLK_out;
F41_CLK_out = DFFEA(F41_CLK_out_lut_out, H7L9, , , , , );

--F41L2Q is dividers:inst|Half_freq:inst21|CLK_out~1
--operation mode is normal

F41L2Q = F41_CLK_out;


--F8_CLK_out is dividers:inst|Half_freq:inst13|CLK_out
--operation mode is normal

F8_CLK_out_lut_out = !F8_CLK_out;
F8_CLK_out = DFFEA(F8_CLK_out_lut_out, H5L9, , , , , );

--F8L2Q is dividers:inst|Half_freq:inst13|CLK_out~1
--operation mode is normal

F8L2Q = F8_CLK_out;


--A1L23 is rtl~14
--operation mode is normal

A1L23 = K1_q[3] & (K1_q[2] # K1_q[1]) # !D1L49;

--A1L54 is rtl~109
--operation mode is normal

A1L54 = K1_q[3] & (K1_q[2] # K1_q[1]) # !D1L49;


--D1L69 is counter_24b:inst3|qout~1653
--operation mode is normal

D1L69 = D1L72 & D1L49;

--D1L101 is counter_24b:inst3|qout~1679
--operation mode is normal

D1L101 = D1L72 & D1L49;


--A1L33 is rtl~25
--operation mode is normal

A1L33 = D1L82 & D1L1 & D1L03 # !D1L69;

--A1L64 is rtl~110
--operation mode is normal

A1L64 = D1L82 & D1L1 & D1L03 # !D1L69;


--A1L43 is rtl~36
--operation mode is normal

A1L43 = D1L1 & D1L03 # !D1L69 # !D1L82;

--A1L74 is rtl~111
--operation mode is normal

A1L74 = D1L1 & D1L03 # !D1L69 # !D1L82;


--A1L53 is rtl~47
--operation mode is normal

A1L53 = D1L1 # !D1L03 # !D1L69 # !D1L82;

--A1L84 is rtl~112
--operation mode is normal

A1L84 = D1L1 # !D1L03 # !D1L69 # !D1L82;


--D1L13 is counter_24b:inst3|always0~168
--operation mode is normal

D1L13 = D1_qout[15] & D1_qout[12] & !D1_qout[14] & !D1_qout[13];

--D1L34 is counter_24b:inst3|always0~183
--operation mode is normal

D1L34 = D1_qout[15] & D1_qout[12] & !D1_qout[14] & !D1_qout[13];

--D1L44 is counter_24b:inst3|always0~184
--operation mode is normal

D1L44 = D1_qout[15] & D1_qout[12] & !D1_qout[14] & !D1_qout[13];


--D1L23 is counter_24b:inst3|always0~169
--operation mode is normal

D1L23 = D1_qout[7] & D1_qout[4] & !D1_qout[6] & !D1_qout[5];

--D1L54 is counter_24b:inst3|always0~185
--operation mode is normal

D1L54 = D1_qout[7] & D1_qout[4] & !D1_qout[6] & !D1_qout[5];

--D1L64 is counter_24b:inst3|always0~186
--operation mode is normal

D1L64 = D1_qout[7] & D1_qout[4] & !D1_qout[6] & !D1_qout[5];


--H3L6Q is dividers:inst|ten_divider:inst3|qout[2]~reg0
--operation mode is normal

H3L6Q_lut_out = H3L6Q $ (H3L4Q & H3L2Q);
H3L6Q = DFFEA(H3L6Q_lut_out, H2L9, Reset, , , , );

--H3L5Q is dividers:inst|ten_divider:inst3|qout[2]~89
--operation mode is normal

H3L5Q = H3L6Q;


--H3L4Q is dividers:inst|ten_divider:inst3|qout[1]~reg0
--operation mode is normal

H3L4Q_lut_out = H3L4Q & (!H3L2Q) # !H3L4Q & H3L2Q & (H3L6Q # !H3L8Q);
H3L4Q = DFFEA(H3L4Q_lut_out, H2L9, Reset, , , , );

--H3L3Q is dividers:inst|ten_divider:inst3|qout[1]~90
--operation mode is normal

H3L3Q = H3L4Q;


--H3L2Q is dividers:inst|ten_divider:inst3|qout[0]~reg0
--operation mode is normal

H3L2Q_lut_out = !H3L2Q;
H3L2Q = DFFEA(H3L2Q_lut_out, H2L9, Reset, , , , );

--H3L1Q is dividers:inst|ten_divider:inst3|qout[0]~91
--operation mode is normal