fcout.cdf

数字频率计 FPGA 用verilog语言编写

/* Quartus II Version 5.0 Build 148 04/26/2005 SJ Full Version */
JedecChain;
	FileRevision(JESD32A);
	DefaultMfr(6E);

	P ActionCode(Ign)
		Device PartName(EPF10K10L84) MfrSpec(OpMask(0) FullPath("fcout.sof"));

ChainEnd;

AlteraBegin;
	ChainType(Download);
AlteraEnd;