📄 fcout.map.rpt
字号:
; I/O pins ; 29 ;
; Maximum fan-out node ; Reset ;
; Maximum fan-out ; 78 ;
; Total fan-out ; 572 ;
; Average fan-out ; 3.38 ;
+-----------------------------------+---------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------------+
; |fcout ; 140 (9) ; 87 ; 0 ; 29 ; 53 (9) ; 40 (0) ; 47 (0) ; 4 (0) ; |fcout ;
; |Half_freq:inst5| ; 1 (1) ; 1 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |fcout|Half_freq:inst5 ;
; |counter_24b:inst3| ; 57 (53) ; 24 ; 0 ; 0 ; 33 (33) ; 0 (0) ; 24 (20) ; 4 (0) ; |fcout|counter_24b:inst3 ;
; |lpm_counter:qout_rtl_0| ; 4 (0) ; 4 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; |fcout|counter_24b:inst3|lpm_counter:qout_rtl_0 ;
; |alt_counter_f10ke:wysi_counter| ; 4 (4) ; 4 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; |fcout|counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter ;
; |display:inst2| ; 24 (24) ; 24 ; 0 ; 0 ; 0 (0) ; 24 (24) ; 0 (0) ; 0 (0) ; |fcout|display:inst2 ;
; |dividers:inst| ; 46 (0) ; 38 ; 0 ; 0 ; 8 (0) ; 15 (0) ; 23 (0) ; 0 (0) ; |fcout|dividers:inst ;
; |Half_freq:inst13| ; 1 (1) ; 1 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |fcout|dividers:inst|Half_freq:inst13 ;
; |Half_freq:inst14| ; 1 (1) ; 1 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |fcout|dividers:inst|Half_freq:inst14 ;
; |Half_freq:inst15| ; 1 (1) ; 1 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |fcout|dividers:inst|Half_freq:inst15 ;
; |Half_freq:inst21| ; 1 (1) ; 1 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |fcout|dividers:inst|Half_freq:inst21 ;
; |Half_freq:inst22| ; 1 (1) ; 1 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |fcout|dividers:inst|Half_freq:inst22 ;
; |Half_freq:inst23| ; 1 (1) ; 1 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |fcout|dividers:inst|Half_freq:inst23 ;
; |Half_freq:inst6| ; 1 (1) ; 1 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |fcout|dividers:inst|Half_freq:inst6 ;
; |Half_freq:inst8| ; 1 (1) ; 1 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |fcout|dividers:inst|Half_freq:inst8 ;
; |div3:inst| ; 3 (3) ; 2 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 2 (2) ; 0 (0) ; |fcout|dividers:inst|div3:inst ;
; |ten_divider:inst12| ; 5 (5) ; 4 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 3 (3) ; 0 (0) ; |fcout|dividers:inst|ten_divider:inst12 ;
; |ten_divider:inst1| ; 5 (5) ; 4 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 3 (3) ; 0 (0) ; |fcout|dividers:inst|ten_divider:inst1 ;
; |ten_divider:inst20| ; 5 (5) ; 4 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 3 (3) ; 0 (0) ; |fcout|dividers:inst|ten_divider:inst20 ;
; |ten_divider:inst2| ; 5 (5) ; 4 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 3 (3) ; 0 (0) ; |fcout|dividers:inst|ten_divider:inst2 ;
; |ten_divider:inst3| ; 5 (5) ; 4 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 3 (3) ; 0 (0) ; |fcout|dividers:inst|ten_divider:inst3 ;
; |ten_divider:inst4| ; 5 (5) ; 4 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 3 (3) ; 0 (0) ; |fcout|dividers:inst|ten_divider:inst4 ;
; |ten_divider:inst5| ; 5 (5) ; 4 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 3 (3) ; 0 (0) ; |fcout|dividers:inst|ten_divider:inst5 ;
; |mode:inst4| ; 3 (3) ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; 0 (0) ; |fcout|mode:inst4 ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 87 ;
; Number of registers using Synchronous Clear ; 4 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 78 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 4 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: counter_24b:inst3|lpm_counter:qout_rtl_0 ;
+------------------------+---------+--------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+---------+--------------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 4 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; DEVICE_FAMILY ; FLEX10K ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+---------+--------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/fcout/fcout.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Thu Apr 05 22:27:24 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fcout -c fcout
Info: Found 1 design units, including 1 entities, in source file Half_freq.v
Info: Found entity 1: Half_freq
Warning: (10268) Verilog HDL information at ten_divider.v(8): Always Construct contains both blocking and non-blocking assignments
Info: Found 1 design units, including 1 entities, in source file ten_divider.v
Info: Found entity 1: ten_divider
Info: Found 1 design units, including 1 entities, in source file counter_24b.v
Info: Found entity 1: counter_24b
Warning: (10268) Verilog HDL information at div3.v(8): Always Construct contains both blocking and non-blocking assignments
Info: Found 1 design units, including 1 entities, in source file div3.v
Info: Found entity 1: div3
Info: Found 1 design units, including 1 entities, in source file display.v
Info: Found entity 1: display
Info: Found 1 design units, including 1 entities, in source file mode.v
Info: Found entity 1: mode
Info: Found 1 design units, including 1 entities, in source file dividers.bdf
Info: Found entity 1: dividers
Info: Found 1 design units, including 1 entities, in source file fcout.bdf
Info: Found entity 1: fcout
Info: Elaborating entity "fcout" for the top level hierarchy
Info: Elaborating entity "display" for hierarchy "display:inst2"
Info: Elaborating entity "mode" for hierarchy "mode:inst4"
Warning: Verilog HDL assignment warning at mode.v(10): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at mode.v(11): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL Always Construct warning at mode.v(31): variable "clock_hhalf" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at mode.v(33): variable "clock_hhalf" is read inside the Always Construct but isn't in the Always Construct's Event Control
Info: Elaborating entity "dividers" for hierarchy "dividers:inst"
Info: Elaborating entity "Half_freq" for hierarchy "dividers:inst|Half_freq:inst7"
Info: Elaborating entity "ten_divider" for hierarchy "dividers:inst|ten_divider:inst3"
Warning: Verilog HDL assignment warning at ten_divider.v(13): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at ten_divider.v(15): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "div3" for hierarchy "dividers:inst|div3:inst"
Warning: Verilog HDL assignment warning at div3.v(13): truncated value with size 32 to match size of target (2)
Warning: Verilog HDL assignment warning at div3.v(14): truncated value with size 32 to match size of target (2)
Info: Elaborating entity "counter_24b" for hierarchy "counter_24b:inst3"
Info: Inferred 1 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter_24b:inst3|qout[0]~332"
Info: Found 1 design units, including 1 entities, in source file ../altera/quartus50/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file ../altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf
Info: Found entity 1: alt_counter_f10ke
Info: Implemented 169 device resources after synthesis - the final resource count might be different
Info: Implemented 5 input pins
Info: Implemented 24 output pins
Info: Implemented 140 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
Info: Processing ended: Thu Apr 05 22:27:30 2007
Info: Elapsed time: 00:00:07
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -