seltime.vhd

来自「关于数字钟的实现」· VHDL 代码 · 共 38 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity SELTIME is
  port(
        clk:in std_logic;------扫描时钟
        secm1,secm0,sec1,sec0,min1,min0,h1,h0:in std_logic_vector(3 downto 0);-----分别为秒个位/时位；分个位/
        daout:out std_logic_vector(3 downto 0);----------------输出
        sel:out std_logic_vector(2 downto 0));-----位选信号
end SELTIME;
architecture fun of SELTIME is
   signal count:std_logic_vector(2 downto 0);----计数信号
begin
   sel<=count;
   process(clk)
          begin
              if(clk'event and clk='1') then
                 if(count>="111") then
                    count<="000";
                  else
                    count<=count+1;
                  end if;
               end if;
  case count is
  when"111"=>daout<= secm0;----秒个位
  when"110"=>daout<= secm1;----秒十位
  when"101"=>daout<= sec0;----分个位
  when"100"=>daout<= sec1;----分十位
  when"011"=>daout<=min0;   ----时个位
  when"010"=>daout<=min1;----时十位
  when"001"=>daout<=h0;
  when others =>daout<=h1;
  end case;
  end process;
end fun;