cpi.v

verilog实现的简易通用型CPI接口

module CPI(
			//input
			clk,
			Rst_n,
			frame,
			irdy,
			ad_high,
			ad_low,
			c_be,
			
			//output
			trdy,
			devsel,
			cs,
			r_w,
			addr
			);
	input clk,Rst_n;
	input frame,irdy;
	input [31:24] ad_high;
	input [12:0]	ad_low;
	input [3:0]	c_be;
	
	output trdy,devsel;
	output cs,r_w;
	output [12:0]	addr;
	
	reg [12:0]	addr_map;
	reg read,write,cs_map;
	reg [2:0]	state;
	
	parameter 
				S0 =  3'd0,
				S1 =  3'd1,
				S2 =  3'd2,
				S3 =  3'd3,
				S4 =  3'd4,
				S5 =  3'd5;
		
		// 读，写，从设备的控制		
	always @ (posedge clk)	
		if( (c_be==4'd6) && (ad_high == 8'd50) && (state == S1))
			begin
				read <= 1'b0;
				write <= 1'b1;
				cs_map <= 1'b0;
			end
		else if( (c_be == 4'd7) && (ad_high == 8'd50) && (state == S1))
			begin
				read <= 1'b1;
				write <= 1'b0;
				cs_map <= 1'b0;
			end 
		else if(state == S0)
			begin	
				read <= 1'b1;
				write <= 1'b1;
				cs_map <= 1'b1;
			end
	
	//操作地址的递增
	always @ (negedge clk)
		if(state == S1)
			addr_map <= ad_low;
		else if(state == S3)
			addr_map <= addr_map + 1'b1;
			
	//操作信号的产生
	assign addr = ((state == S3) || (state == S4))? addr_map:13'bzzzzzzzzzzzzz;
	assign trdy = ((state == S3) || (state == S4) || (state == S5))? 1'b0:1'b1;
	assign devsel = ((state == S3) || (state == S4))? 1'b0:1'b1;
	assign r_w  = ((write == 1'b0) && ((state == S3) ||( state == S4)))? ~clk: 1'b1;
	assign cs   = ((state == S3) || (state == S4))? 1'b0 : 1'b1;
	
	always @ (negedge clk)
		if(Rst_n == 1'b0)
			state <= S0;
		else
			case(state)
				S0:
					begin
						if((frame == 1'b1) && (irdy == 1'b1))
							state <= S0;
						else if((frame == 1'b0) && (irdy == 1'b1))
							state <= S1;
					end
				S1:
					begin
						if((cs_map == 1'b1) || ((read == 1'b1) && (write == 1'b1)))
							state <= S0;
						else if((irdy == 1'b1) && (read == 1'b0))
							state <= S2;
						else if((frame == 1'b0) && (irdy == 1'b0) && (write == 1'b0))
							state <= S3;
						else if((frame == 1'b1) && (irdy == 1'b0) && (write == 1'b0))
							state <= S4;
					end
				S2:
					begin
						if((frame == 1'b1) && (irdy == 1'b1))
							state <= S0;
						else if((frame == 1'b0) && (irdy == 1'b0) && (read == 1'b0))
							state <= S3;
						else if((frame == 1'b1) && (irdy == 1'b0) && (read == 1'b0))
							state <= S4; 
					end
				S3:
					begin
						if((frame == 1'b1) && (irdy == 1'b1))
							state <= S0;
						else if((frame == 1'b0) && (irdy == 1'b1))
							state <= S5;
						else if((frame == 1'b1) && (irdy == 1'b0))
							state <= S4;
						else if((frame == 1'b0) && (irdy == 1'b0))
							state <= S3;
					end
				S4:
					begin
						if((frame == 1'b1) && (irdy == 1'b1))
							state <= S0;
						else if((frame == 1'b1) && (irdy == 1'b0))
							state <= S4;
					end
				S5:
					begin
						if((frame == 1'b1) && (irdy == 1'b1))
							state <= S0;
						else if((frame == 1'b0) && (irdy == 1'b0))
							state <= S3;
						else if((frame == 1'b1) && (irdy == 1'b0))
							state <= S4;
						else
							state <= S5;
					end
				default:
					state <= S0;
			endcase
	endmodule