paobiao.v

来自「verilog实现的数字跑表 精确到10ms」· Verilog 代码 · 共 73 行

module paobiao(reset,clk,Pause,MSH,MSL,SH,SL,MH,ML);
input   reset,clk,Pause;
output [3:0]   MSH,MSL,MH,ML,SH,SL;

reg [3:0]   MSH,MSL,MH,ML,SH,SL;
reg   cn1,cn2;
always @ (posedge clk)
   if(!reset)
      begin
         cn1 <= 1'b0;
         {MSH,MSL} <= 8'd0;
      end
    else
       if(!Pause)        //pause=0 start to count
         begin
            if(MSL==9)
               begin
                  MSL <= 4'd0;
                  if(MSH==9)
                     begin
                         MSH <= 4'd0;
                         cn1 <= 1'b1;
                      end
                  else
                     MSH <= MSH +1'b1;
                end
            else
            begin
               MSL <= MSL + 1'b1; 
               cn1 <= 1'b0;
           end  
         end

always @ (posedge cn1)
   if(!reset)
      {SH,SL} <= 8'd0;
    else
       if(SL==9)
       begin
           SL <= 4'd0;
           if(SH==5)
              begin
                  SH <= 4'd0;
                  cn2 <= 1'b1;
              end
            else
             SH <= SH +1'b1;
       end
       else
        begin
          SL <= SL + 1'b1;
          cn2 <= 1'd0;
       end
    
always @ (posedge cn2)
   if(!reset)
      {MH,ML} <= 8'd0;
  else
      if(ML==9)
          begin
           ML <= 4'd0;
           if(MH==5)
              begin
                  MH <= 4'd0;
              end
            else
             MH <= MH +1'b1;
          end
       else
          ML <= ML + 1'b1;    
    
endmodule