stmch1.map.qmsg

来自「4位可逆计数器：将50MHz的时钟进行 分频后的结果作为时钟控制」· QMSG 代码 · 共 7 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jan 04 21:17:47 2008 " "Info: Processing started: Fri Jan 04 21:17:47 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off stmch1 -c stmch1 --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off stmch1 -c stmch1 --generate_functional_sim_netlist" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "stmch1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file stmch1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 stmch1-behave " "Info: Found design unit 1: stmch1-behave" {  } { { "stmch1.vhd" "" { Text "C:/微机实验报告/evelyn/ex (3)/stmch1.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 stmch1 " "Info: Found entity 1: stmch1" {  } { { "stmch1.vhd" "" { Text "C:/微机实验报告/evelyn/ex (3)/stmch1.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "stmch1 " "Info: Elaborating entity \"stmch1\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jan 04 21:17:52 2008 " "Info: Processing ended: Fri Jan 04 21:17:52 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}