stmch1.fit.qmsg

4位可逆计数器：将50MHz的时钟进行 分频后的结果作为时钟控制

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jan 04 17:21:41 2008 " "Info: Processing started: Fri Jan 04 17:21:41 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off stmch1 -c stmch1 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off stmch1 -c stmch1" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "stmch1 EP2C35F672C6 " "Info: Selected device EP2C35F672C6 for design \"stmch1\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F672C6 " "Info: Device EP2C50F672C6 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C70F672C6 " "Info: Device EP2C70F672C6 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN A13 (CLK9, LVDSCLK4p, Input)) " "Info: Automatically promoted node clk (placed in PIN A13 (CLK9, LVDSCLK4p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G10 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G10" {  } {  } 0}  } { { "stmch1.vhd" "" { Text "C:/微机实验报告/evelyn/ex (3)/stmch1.vhd" 5 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "" { clk } "NODE_NAME" } "" } } { "C:/微机实验报告/evelyn/ex (3)/stmch1.fld" "" { Floorplan "C:/微机实验报告/evelyn/ex (3)/stmch1.fld" "" "" { clk } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "0.716 ns register register " "Info: Estimated most critical path is register to register delay of 0.716 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state.s0 1 REG LAB_X3_Y35 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X3_Y35; Fanout = 1; REG Node = 'state.s0'" {  } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "" { state.s0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.477 ns) + CELL(0.153 ns) 0.630 ns Select~14 2 COMB LAB_X3_Y35 2 " "Info: 2: + IC(0.477 ns) + CELL(0.153 ns) = 0.630 ns; Loc. = LAB_X3_Y35; Fanout = 2; COMB Node = 'Select~14'" {  } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "0.630 ns" { state.s0 Select~14 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 0.716 ns state.s1 3 REG LAB_X3_Y35 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 0.716 ns; Loc. = LAB_X3_Y35; Fanout = 2; REG Node = 'state.s1'" {  } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "0.086 ns" { Select~14 state.s1 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.239 ns 33.38 % " "Info: Total cell delay = 0.239 ns ( 33.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.477 ns 66.62 % " "Info: Total interconnect delay = 0.477 ns ( 66.62 % )" {  } {  } 0}  } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "0.716 ns" { state.s0 Select~14 state.s1 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Warning" "WDAT_PRELIMINARY_TIMING" "EP2C35F672C6 " "Warning: Timing characteristics of device EP2C35F672C6 are preliminary" {  } {  } 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "1 " "Warning: Found 1 output pins without output pin load capacitance assignment" { { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "out1 0 " "Warning: Pin \"out1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0}  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jan 04 17:22:03 2008 " "Info: Processing ended: Fri Jan 04 17:22:03 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:22 " "Info: Elapsed time: 00:00:22" {  } {  } 0}  } {  } 0}