📄 stmch1.fit.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--state.s1 is state.s1 at LCFF_X3_Y35_N1
state.s1 = DFFEAS(A1L6, GLOBAL(A1L2), rst, , , , , , );
--state.s0 is state.s0 at LCFF_X3_Y35_N7
state.s0 = DFFEAS(A1L8, GLOBAL(A1L2), rst, , !in1, , , , );
--A1L6 is Select~14 at LCCOMB_X3_Y35_N0
A1L6 = in1 & (state.s1) # !in1 & !state.s0;
--A1L8 is state.s0~6 at LCCOMB_X3_Y35_N6
A1L8 = !state.s1;
--in1 is in1 at PIN_A4
--operation mode is input
in1 = INPUT();
--clk is clk at PIN_A13
--operation mode is input
clk = INPUT();
--rst is rst at PIN_A6
--operation mode is input
rst = INPUT();
--out1 is out1 at PIN_A5
--operation mode is output
out1 = OUTPUT(A1L6);
--A1L2 is clk~clkctrl at CLKCTRL_G10
A1L2 = cycloneii_clkctrl(.INCLK[0] = clk) WITH (clock_type = "Global Clock");
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