stmch1.sim.rpt

4位可逆计数器：将50MHz的时钟进行 分频后的结果作为时钟控制

Simulator report for stmch1
Fri Jan 04 21:18:02 2008
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Simulator Summary
  3. Simulator Settings
  4. Simulation Waveforms
  5. Simulator INI Usage
  6. Simulator Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+--------------------------------------------+
; Simulator Summary                          ;
+-----------------------------+--------------+
; Type                        ; Value        ;
+-----------------------------+--------------+
; Simulation Start Time       ; 0 ps         ;
; Simulation End Time         ; 1.0 us       ;
; Simulation Netlist Size     ; 10 nodes     ;
; Simulation Coverage         ;      66.67 % ;
; Total Number of Transitions ; 708          ;
+-----------------------------+--------------+


+-----------------------------------------------------------------+
; Simulator Settings                                              ;
+-------------------------------------------------------+---------+
; Option                                                ; Setting ;
+-------------------------------------------------------+---------+
; Simulation mode                                       ; Timing  ;
; Start time                                            ; 0ns     ;
; Add pins automatically to simulation output waveforms ; On      ;
; Check outputs                                         ; Off     ;
; Report simulation coverage                            ; On      ;
; Detect setup and hold time violations                 ; Off     ;
; Detect glitches                                       ; Off     ;
; Automatically save/load simulation netlist            ; Off     ;
; Disable timing delays in Timing Simulation            ; Off     ;
; Generate Signal Activity File                         ; Off     ;
+-------------------------------------------------------+---------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Jan 04 21:18:01 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off stmch1 -c stmch1
Warning: Can't display state machine states -- register holding state machine bit "|stmch1|state.sx" was synthesized away
Info: Simulation coverage is      66.67 %
Info: Number of transitions in simulation is 708
Info: Quartus II Simulator was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Jan 04 21:18:02 2008
    Info: Elapsed time: 00:00:02
Info: You are using the Quartus II software in "Evaluation Mode". You have 10 days left (until 14-jan-2008) before compilation and simulation support are disabled.