stmch1.flow.rpt

4位可逆计数器：将50MHz的时钟进行 分频后的结果作为时钟控制

Flow report for stmch1
Fri Jan 04 17:22:13 2008
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Elapsed Time
  5. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Flow Summary                                                                  ;
+------------------------------------+------------------------------------------+
; Flow Status                        ; Successful - Fri Jan 04 17:22:13 2008    ;
; Quartus II Version                 ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name                      ; stmch1                                   ;
; Top-level Entity Name              ; stmch1                                   ;
; Family                             ; Cyclone II                               ;
; Device                             ; EP2C35F672C6                             ;
; Timing Models                      ; Preliminary                              ;
; Met timing requirements            ; Yes                                      ;
; Total logic elements               ; 2 / 33,216 ( < 1 % )                     ;
; Total registers                    ; 2                                        ;
; Total pins                         ; 4 / 475 ( < 1 % )                        ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 0 / 483,840 ( 0 % )                      ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % )                           ;
; Total PLLs                         ; 0 / 4 ( 0 % )                            ;
+------------------------------------+------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 01/04/2008 17:21:36 ;
; Main task         ; Compilation         ;
; Revision Name     ; stmch1              ;
+-------------------+---------------------+


+-------------------------------------+
; Flow Elapsed Time                   ;
+----------------------+--------------+
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:03     ;
; Fitter               ; 00:00:22     ;
; Assembler            ; 00:00:01     ;
; Timing Analyzer      ; 00:00:01     ;
; Total                ; 00:00:27     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off stmch1 -c stmch1
quartus_fit --read_settings_files=off --write_settings_files=off stmch1 -c stmch1
quartus_asm --read_settings_files=off --write_settings_files=off stmch1 -c stmch1
quartus_tan --read_settings_files=off --write_settings_files=off stmch1 -c stmch1 --timing_analysis_only