my2.txt

4位可逆计数器：将50MHz的时钟进行 分频后的结果作为时钟控制

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY majl IS
    PORT (a,b,c,d,e:IN BIT;
m:out BIT);
end majl;
ARCHITECTURE CONCURRENT of majl is 
BEGIN
  WITH a&b&c&d&e SELECT
m<='1' when "11111"|"11110"|"11101"|"11011"|"10111"|"01111"|"11100"|"11001"|"10011"|"00111"|"01011"|"01101"|"01110"|"10101"|"10110"|"11010",
 '0' when others ;
end concurrent;