daima.txt

4位可逆计数器：将50MHz的时钟进行 分频后的结果作为时钟控制

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
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entity clkdiv is
   port(clk: in std_logic;
   output: std_logic;
   end clkdiv;
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architecture divide of clkdiv is
begin
   process(clk)
 begin
      if (clk'event and clk='1') then
         count<=count+'1';
         
       end if;
		output<=count(24);
    end process;
end divide;




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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
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entity counter is
   port(clk: in std_logic;
        sw17: in std_logic;
        sw: in std_logic_vector(3 downto 0);
        key3:in std_logic;
        ledr: out std_logic_vector(3 downto 0);
        led17: out std_logic);
   end counter;
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architecture count of counter is
signal count: std_logic_VECTOR(24 DOWNTO 0);
signal output: std_logic;
signal out1: std_logic_vector(3 downto 0):=sw;
COMPONENT devide25 
	PORT (clk,rst : IN STD_LOGIC;
		  output  : OUT STD_LOGIC);
END COMPONENT;
BEGIN
	unit : devide25 PORT MAP (clk=>clkin,rst=>rst,output=>actualclk);
	
   process(sw17,output,key3)
   begin
     if(sw17='1') then
        if(key3='0') then--0 or 1?
        out1<="0000";
		elsif (output'event and output='1') then
		out1<=out1+'1';
		end if;
	elsif(sw17='0') then
	    if(key3='0') then
        out1<="1111";
		elsif (output'event and output='1') then
		out1<=out1-'1';
		end if;
	end if;
	end process;
	led17<=sw17;
	ledr<=out1;
end count;
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