stmch1.map.eqn

4位可逆计数器：将50MHz的时钟进行 分频后的结果作为时钟控制

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--state.s1 is state.s1
state.s1 = DFFEAS(A1L5, clk, rst,  ,  ,  ,  ,  ,  );


--state.s0 is state.s0
state.s0 = DFFEAS(A1L7, clk, rst,  , !in1,  ,  ,  ,  );


--A1L5 is Select~14
A1L5 = in1 & state.s1 # !in1 & (!state.s0);


--A1L7 is state.s0~6
A1L7 = !state.s1;


--in1 is in1
--operation mode is input

in1 = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--rst is rst
--operation mode is input

rst = INPUT();


--out1 is out1
--operation mode is output

out1 = OUTPUT(A1L5);