sample.tan.rpt

运行在FPGA上的Verilog程序(实现对ADC的控制)...

; Slack ; Required tco ; Actual tco ; From                 ; To         ; From Clock ;
+-------+--------------+------------+----------------------+------------+------------+
; N/A   ; None         ; 12.555 ns  ; dataOut[1]$latch     ; dataOut[1] ; clk        ;
; N/A   ; None         ; 12.447 ns  ; dataOut[6]$latch     ; dataOut[6] ; clk        ;
; N/A   ; None         ; 12.409 ns  ; dataOut[4]$latch     ; dataOut[4] ; clk        ;
; N/A   ; None         ; 12.348 ns  ; dataOut[3]$latch     ; dataOut[3] ; clk        ;
; N/A   ; None         ; 11.721 ns  ; dataOut[5]$latch     ; dataOut[5] ; clk        ;
; N/A   ; None         ; 11.237 ns  ; dataOut[7]$latch     ; dataOut[7] ; clk        ;
; N/A   ; None         ; 11.072 ns  ; dataOut[0]$latch     ; dataOut[0] ; clk        ;
; N/A   ; None         ; 10.929 ns  ; dataOut[2]$latch     ; dataOut[2] ; clk        ;
; N/A   ; None         ; 9.338 ns   ; current_state.state3 ; OE         ; clk        ;
; N/A   ; None         ; 8.755 ns   ; current_state.state1 ; ALE        ; clk        ;
; N/A   ; None         ; 8.752 ns   ; current_state.state4 ; OE         ; clk        ;
; N/A   ; None         ; 8.671 ns   ; current_state.state4 ; dataINT    ; clk        ;
; N/A   ; None         ; 8.414 ns   ; current_state.state1 ; START      ; clk        ;
+-------+--------------+------------+----------------------+------------+------------+


+---------------------------------------------------------------------------------------+
; th                                                                                    ;
+---------------+-------------+-----------+-----------+----------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From      ; To                   ; To Clock ;
+---------------+-------------+-----------+-----------+----------------------+----------+
; N/A           ; None        ; -0.139 ns ; dataIn[4] ; dataOut[4]$latch     ; clk      ;
; N/A           ; None        ; -0.364 ns ; dataIn[1] ; dataOut[1]$latch     ; clk      ;
; N/A           ; None        ; -0.606 ns ; dataIn[3] ; dataOut[3]$latch     ; clk      ;
; N/A           ; None        ; -0.742 ns ; dataIn[6] ; dataOut[6]$latch     ; clk      ;
; N/A           ; None        ; -1.142 ns ; dataIn[5] ; dataOut[5]$latch     ; clk      ;
; N/A           ; None        ; -1.342 ns ; dataIn[7] ; dataOut[7]$latch     ; clk      ;
; N/A           ; None        ; -1.360 ns ; dataIn[0] ; dataOut[0]$latch     ; clk      ;
; N/A           ; None        ; -1.741 ns ; dataIn[2] ; dataOut[2]$latch     ; clk      ;
; N/A           ; None        ; -5.073 ns ; EOC       ; current_state.state2 ; clk      ;
; N/A           ; None        ; -5.074 ns ; EOC       ; current_state.state3 ; clk      ;
; N/A           ; None        ; -5.771 ns ; enable    ; current_state.state1 ; clk      ;
; N/A           ; None        ; -5.771 ns ; enable    ; current_state.state0 ; clk      ;
; N/A           ; None        ; -5.771 ns ; enable    ; current_state.state3 ; clk      ;
; N/A           ; None        ; -5.771 ns ; enable    ; current_state.state2 ; clk      ;
; N/A           ; None        ; -5.771 ns ; enable    ; current_state.state4 ; clk      ;
+---------------+-------------+-----------+-----------+----------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Sun Jan 07 09:38:12 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sample -c sample --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "dataOut[0]$latch" is a latch
    Warning: Node "dataOut[1]$latch" is a latch
    Warning: Node "dataOut[2]$latch" is a latch
    Warning: Node "dataOut[3]$latch" is a latch
    Warning: Node "dataOut[4]$latch" is a latch
    Warning: Node "dataOut[5]$latch" is a latch
    Warning: Node "dataOut[6]$latch" is a latch
    Warning: Node "dataOut[7]$latch" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "current_state.state4" as buffer
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "current_state.state2" and destination register "current_state.state2"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.040 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y6_N8; Fanout = 2; REG Node = 'current_state.state2'
            Info: 2: + IC(0.562 ns) + CELL(0.478 ns) = 1.040 ns; Loc. = LC_X8_Y6_N8; Fanout = 2; REG Node = 'current_state.state2'
            Info: Total cell delay = 0.478 ns ( 45.96 % )
            Info: Total interconnect delay = 0.562 ns ( 54.04 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.738 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(0.558 ns) + CELL(0.711 ns) = 2.738 ns; Loc. = LC_X8_Y6_N8; Fanout = 2; REG Node = 'current_state.state2'
                Info: Total cell delay = 2.180 ns ( 79.62 % )
                Info: Total interconnect delay = 0.558 ns ( 20.38 % )
            Info: - Longest clock path from clock "clk" to source register is 2.738 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(0.558 ns) + CELL(0.711 ns) = 2.738 ns; Loc. = LC_X8_Y6_N8; Fanout = 2; REG Node = 'current_state.state2'
                Info: Total cell delay = 2.180 ns ( 79.62 % )
                Info: Total interconnect delay = 0.558 ns ( 20.38 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "current_state.state1" (data pin = "enable", clock pin = "clk") is 5.823 ns
    Info: + Longest pin to register delay is 8.524 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_143; Fanout = 5; PIN Node = 'enable'
        Info: 2: + IC(6.182 ns) + CELL(0.867 ns) = 8.524 ns; Loc. = LC_X8_Y6_N5; Fanout = 3; REG Node = 'current_state.state1'
        Info: Total cell delay = 2.342 ns ( 27.48 % )
        Info: Total interconnect delay = 6.182 ns ( 72.52 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.738 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(0.558 ns) + CELL(0.711 ns) = 2.738 ns; Loc. = LC_X8_Y6_N5; Fanout = 3; REG Node = 'current_state.state1'
        Info: Total cell delay = 2.180 ns ( 79.62 % )
        Info: Total interconnect delay = 0.558 ns ( 20.38 % )
Info: tco from clock "clk" to destination pin "dataOut[1]" through register "dataOut[1]$latch" is 12.555 ns
    Info: + Longest clock path from clock "clk" to source register is 7.085 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(0.558 ns) + CELL(0.935 ns) = 2.962 ns; Loc. = LC_X8_Y6_N2; Fanout = 11; REG Node = 'current_state.state4'
        Info: 3: + IC(4.009 ns) + CELL(0.114 ns) = 7.085 ns; Loc. = LC_X8_Y4_N2; Fanout = 1; REG Node = 'dataOut[1]$latch'
        Info: Total cell delay = 2.518 ns ( 35.54 % )
        Info: Total interconnect delay = 4.567 ns ( 64.46 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 5.470 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y4_N2; Fanout = 1; REG Node = 'dataOut[1]$latch'
        Info: 2: + IC(3.362 ns) + CELL(2.108 ns) = 5.470 ns; Loc. = PIN_121; Fanout = 0; PIN Node = 'dataOut[1]'
        Info: Total cell delay = 2.108 ns ( 38.54 % )
        Info: Total interconnect delay = 3.362 ns ( 61.46 % )
Info: th for register "dataOut[4]$latch" (data pin = "dataIn[4]", clock pin = "clk") is -0.139 ns
    Info: + Longest clock path from clock "clk" to destination register is 7.102 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(0.558 ns) + CELL(0.935 ns) = 2.962 ns; Loc. = LC_X8_Y6_N2; Fanout = 11; REG Node = 'current_state.state4'
        Info: 3: + IC(4.026 ns) + CELL(0.114 ns) = 7.102 ns; Loc. = LC_X8_Y7_N3; Fanout = 1; REG Node = 'dataOut[4]$latch'
        Info: Total cell delay = 2.518 ns ( 35.45 % )
        Info: Total interconnect delay = 4.584 ns ( 64.55 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: - Shortest pin to register delay is 7.241 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_47; Fanout = 1; PIN Node = 'dataIn[4]'
        Info: 2: + IC(5.474 ns) + CELL(0.292 ns) = 7.241 ns; Loc. = LC_X8_Y7_N3; Fanout = 1; REG Node = 'dataOut[4]$latch'
        Info: Total cell delay = 1.767 ns ( 24.40 % )
        Info: Total interconnect delay = 5.474 ns ( 75.60 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 11 warnings
    Info: Processing ended: Sun Jan 07 09:38:12 2007
    Info: Elapsed time: 00:00:01