sample.map.rpt

运行在FPGA上的Verilog程序(实现对ADC的控制)...

;     -- 3 input functions                    ; 9                    ;
;     -- 2 input functions                    ; 2                    ;
;     -- 1 input functions                    ; 2                    ;
;     -- 0 input functions                    ; 0                    ;
;         -- Combinational cells for routing  ; 0                    ;
;                                             ;                      ;
; Logic elements by mode                      ;                      ;
;     -- normal mode                          ; 14                   ;
;     -- arithmetic mode                      ; 0                    ;
;     -- qfbk mode                            ; 0                    ;
;     -- register cascade mode                ; 0                    ;
;     -- synchronous clear/load mode          ; 0                    ;
;     -- asynchronous clear/load mode         ; 5                    ;
;                                             ;                      ;
; Total registers                             ; 5                    ;
; I/O pins                                    ; 25                   ;
; Maximum fan-out node                        ; current_state.state4 ;
; Maximum fan-out                             ; 11                   ;
; Total fan-out                               ; 61                   ;
; Average fan-out                             ; 1.56                 ;
+---------------------------------------------+----------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |sample                    ; 14 (14)     ; 5            ; 0           ; 25   ; 0            ; 9 (9)        ; 1 (1)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |sample             ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |sample|current_state                                                                                                   ;
+----------------------+----------------------+----------------------+----------------------+----------------------+----------------------+
; Name                 ; current_state.state1 ; current_state.state2 ; current_state.state3 ; current_state.state0 ; current_state.state4 ;
+----------------------+----------------------+----------------------+----------------------+----------------------+----------------------+
; current_state.state0 ; 0                    ; 0                    ; 0                    ; 0                    ; 0                    ;
; current_state.state3 ; 0                    ; 0                    ; 1                    ; 1                    ; 0                    ;
; current_state.state2 ; 0                    ; 1                    ; 0                    ; 1                    ; 0                    ;
; current_state.state1 ; 1                    ; 0                    ; 0                    ; 1                    ; 0                    ;
; current_state.state4 ; 0                    ; 0                    ; 0                    ; 1                    ; 1                    ;
+----------------------+----------------------+----------------------+----------------------+----------------------+----------------------+


+---------------------------------------------------+
; User-Specified and Inferred Latches               ;
+-----------------------------------------------+---+
; Latch Name                                    ;   ;
+-----------------------------------------------+---+
; dataOut[0]$latch                              ;   ;
; dataOut[1]$latch                              ;   ;
; dataOut[2]$latch                              ;   ;
; dataOut[3]$latch                              ;   ;
; dataOut[4]$latch                              ;   ;
; dataOut[5]$latch                              ;   ;
; dataOut[6]$latch                              ;   ;
; dataOut[7]$latch                              ;   ;
; Number of user-specified and inferred latches ; 8 ;
+-----------------------------------------------+---+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 5     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 5     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 5     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |sample ;
+----------------+-------+-----------------------------------------------+
; Parameter Name ; Value ; Type                                          ;
+----------------+-------+-----------------------------------------------+
; state0         ; 000   ; Binary                                        ;
; state1         ; 001   ; Binary                                        ;
; state2         ; 010   ; Binary                                        ;
; state3         ; 011   ; Binary                                        ;
; state4         ; 100   ; Binary                                        ;
+----------------+-------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Sun Jan 07 09:37:55 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sample -c sample
Warning (10268): Verilog HDL information at sample.v(23): Always Construct contains both blocking and non-blocking assignments
Info: Found 1 design units, including 1 entities, in source file sample.v
    Info: Found entity 1: sample
Info: Elaborating entity "sample" for the top level hierarchy
Warning (10235): Verilog HDL Always Construct warning at sample.v(67): variable "dataIn" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10240): Verilog HDL Always Construct warning at sample.v(30): variable "ADDA" may not be assigned a new value in every possible path through the Always Construct.  Variable "ADDA" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10240): Verilog HDL Always Construct warning at sample.v(30): variable "dataOut" may not be assigned a new value in every possible path through the Always Construct.  Variable "dataOut" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: State machine "|sample|current_state" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|sample|current_state"
Info: Encoding result for state machine "|sample|current_state"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "current_state.state1"
        Info: Encoded state bit "current_state.state2"
        Info: Encoded state bit "current_state.state3"
        Info: Encoded state bit "current_state.state0"
        Info: Encoded state bit "current_state.state4"
    Info: State "|sample|current_state.state0" uses code string "00000"
    Info: State "|sample|current_state.state3" uses code string "00110"
    Info: State "|sample|current_state.state2" uses code string "01010"
    Info: State "|sample|current_state.state1" uses code string "10010"
    Info: State "|sample|current_state.state4" uses code string "00011"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "ADDA" stuck at VCC
Info: Implemented 39 device resources after synthesis - the final resource count might be different
    Info: Implemented 12 input pins
    Info: Implemented 13 output pins
    Info: Implemented 14 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Processing ended: Sun Jan 07 09:37:57 2007
    Info: Elapsed time: 00:00:03