sample.smp_dump.txt

来自「运行在FPGA上的Verilog程序(实现对ADC的控制)...」· 文本 代码 · 共 9 行

State Machine - |sample|current_state
Name current_state.state1 current_state.state2 current_state.state3 current_state.state0 current_state.state4 
current_state.state0 0 0 0 0 0 
current_state.state3 0 0 1 1 0 
current_state.state2 0 1 0 1 0 
current_state.state1 1 0 0 1 0 
current_state.state4 0 0 0 1 1