sample.tan.qmsg

运行在FPGA上的Verilog程序(实现对ADC的控制)...

{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataOut\[1\] dataOut\[1\]\$latch 12.555 ns register " "Info: tco from clock \"clk\" to destination pin \"dataOut\[1\]\" through register \"dataOut\[1\]\$latch\" is 12.555 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.085 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.085 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "" { clk } "NODE_NAME" } "" } } { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.935 ns) 2.962 ns current_state.state4 2 REG LC_X8_Y6_N2 11 " "Info: 2: + IC(0.558 ns) + CELL(0.935 ns) = 2.962 ns; Loc. = LC_X8_Y6_N2; Fanout = 11; REG Node = 'current_state.state4'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "1.493 ns" { clk current_state.state4 } "NODE_NAME" } "" } } { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.009 ns) + CELL(0.114 ns) 7.085 ns dataOut\[1\]\$latch 3 REG LC_X8_Y4_N2 1 " "Info: 3: + IC(4.009 ns) + CELL(0.114 ns) = 7.085 ns; Loc. = LC_X8_Y4_N2; Fanout = 1; REG Node = 'dataOut\[1\]\$latch'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "4.123 ns" { current_state.state4 dataOut[1]$latch } "NODE_NAME" } "" } } { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.518 ns ( 35.54 % ) " "Info: Total cell delay = 2.518 ns ( 35.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.567 ns ( 64.46 % ) " "Info: Total interconnect delay = 4.567 ns ( 64.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "7.085 ns" { clk current_state.state4 dataOut[1]$latch } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.085 ns" { clk clk~out0 current_state.state4 dataOut[1]$latch } { 0.000ns 0.000ns 0.558ns 4.009ns } { 0.000ns 1.469ns 0.935ns 0.114ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.470 ns + Longest register pin " "Info: + Longest register to pin delay is 5.470 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dataOut\[1\]\$latch 1 REG LC_X8_Y4_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y4_N2; Fanout = 1; REG Node = 'dataOut\[1\]\$latch'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "" { dataOut[1]$latch } "NODE_NAME" } "" } } { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.362 ns) + CELL(2.108 ns) 5.470 ns dataOut\[1\] 2 PIN PIN_121 0 " "Info: 2: + IC(3.362 ns) + CELL(2.108 ns) = 5.470 ns; Loc. = PIN_121; Fanout = 0; PIN Node = 'dataOut\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "5.470 ns" { dataOut[1]$latch dataOut[1] } "NODE_NAME" } "" } } { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 38.54 % ) " "Info: Total cell delay = 2.108 ns ( 38.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.362 ns ( 61.46 % ) " "Info: Total interconnect delay = 3.362 ns ( 61.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "5.470 ns" { dataOut[1]$latch dataOut[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.470 ns" { dataOut[1]$latch dataOut[1] } { 0.000ns 3.362ns } { 0.000ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "7.085 ns" { clk current_state.state4 dataOut[1]$latch } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.085 ns" { clk clk~out0 current_state.state4 dataOut[1]$latch } { 0.000ns 0.000ns 0.558ns 4.009ns } { 0.000ns 1.469ns 0.935ns 0.114ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "5.470 ns" { dataOut[1]$latch dataOut[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.470 ns" { dataOut[1]$latch dataOut[1] } { 0.000ns 3.362ns } { 0.000ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "dataOut\[4\]\$latch dataIn\[4\] clk -0.139 ns register " "Info: th for register \"dataOut\[4\]\$latch\" (data pin = \"dataIn\[4\]\", clock pin = \"clk\") is -0.139 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.102 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.102 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "" { clk } "NODE_NAME" } "" } } { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.935 ns) 2.962 ns current_state.state4 2 REG LC_X8_Y6_N2 11 " "Info: 2: + IC(0.558 ns) + CELL(0.935 ns) = 2.962 ns; Loc. = LC_X8_Y6_N2; Fanout = 11; REG Node = 'current_state.state4'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "1.493 ns" { clk current_state.state4 } "NODE_NAME" } "" } } { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.026 ns) + CELL(0.114 ns) 7.102 ns dataOut\[4\]\$latch 3 REG LC_X8_Y7_N3 1 " "Info: 3: + IC(4.026 ns) + CELL(0.114 ns) = 7.102 ns; Loc. = LC_X8_Y7_N3; Fanout = 1; REG Node = 'dataOut\[4\]\$latch'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "4.140 ns" { current_state.state4 dataOut[4]$latch } "NODE_NAME" } "" } } { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.518 ns ( 35.45 % ) " "Info: Total cell delay = 2.518 ns ( 35.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.584 ns ( 64.55 % ) " "Info: Total interconnect delay = 4.584 ns ( 64.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "7.102 ns" { clk current_state.state4 dataOut[4]$latch } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.102 ns" { clk clk~out0 current_state.state4 dataOut[4]$latch } { 0.000ns 0.000ns 0.558ns 4.026ns } { 0.000ns 1.469ns 0.935ns 0.114ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 12 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.241 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.241 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns dataIn\[4\] 1 PIN PIN_47 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_47; Fanout = 1; PIN Node = 'dataIn\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "" { dataIn[4] } "NODE_NAME" } "" } } { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.474 ns) + CELL(0.292 ns) 7.241 ns dataOut\[4\]\$latch 2 REG LC_X8_Y7_N3 1 " "Info: 2: + IC(5.474 ns) + CELL(0.292 ns) = 7.241 ns; Loc. = LC_X8_Y7_N3; Fanout = 1; REG Node = 'dataOut\[4\]\$latch'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "5.766 ns" { dataIn[4] dataOut[4]$latch } "NODE_NAME" } "" } } { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.767 ns ( 24.40 % ) " "Info: Total cell delay = 1.767 ns ( 24.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.474 ns ( 75.60 % ) " "Info: Total interconnect delay = 5.474 ns ( 75.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "7.241 ns" { dataIn[4] dataOut[4]$latch } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.241 ns" { dataIn[4] dataIn[4]~out0 dataOut[4]$latch } { 0.000ns 0.000ns 5.474ns } { 0.000ns 1.475ns 0.292ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "7.102 ns" { clk current_state.state4 dataOut[4]$latch } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.102 ns" { clk clk~out0 current_state.state4 dataOut[4]$latch } { 0.000ns 0.000ns 0.558ns 4.026ns } { 0.000ns 1.469ns 0.935ns 0.114ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "7.241 ns" { dataIn[4] dataOut[4]$latch } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.241 ns" { dataIn[4] dataIn[4]~out0 dataOut[4]$latch } { 0.000ns 0.000ns 5.474ns } { 0.000ns 1.475ns 0.292ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 11 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 07 09:38:12 2007 " "Info: Processing ended: Sun Jan 07 09:38:12 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}