sample.tan.qmsg

运行在FPGA上的Verilog程序(实现对ADC的控制)...

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 2 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "current_state.state4 " "Info: Detected ripple clock \"current_state.state4\" as buffer" {  } { { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "current_state.state4" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register current_state.state2 current_state.state2 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"current_state.state2\" and destination register \"current_state.state2\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.040 ns + Longest register register " "Info: + Longest register to register delay is 1.040 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state.state2 1 REG LC_X8_Y6_N8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y6_N8; Fanout = 2; REG Node = 'current_state.state2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "" { current_state.state2 } "NODE_NAME" } "" } } { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.562 ns) + CELL(0.478 ns) 1.040 ns current_state.state2 2 REG LC_X8_Y6_N8 2 " "Info: 2: + IC(0.562 ns) + CELL(0.478 ns) = 1.040 ns; Loc. = LC_X8_Y6_N8; Fanout = 2; REG Node = 'current_state.state2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "1.040 ns" { current_state.state2 current_state.state2 } "NODE_NAME" } "" } } { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns ( 45.96 % ) " "Info: Total cell delay = 0.478 ns ( 45.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.562 ns ( 54.04 % ) " "Info: Total interconnect delay = 0.562 ns ( 54.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "1.040 ns" { current_state.state2 current_state.state2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.040 ns" { current_state.state2 current_state.state2 } { 0.000ns 0.562ns } { 0.000ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.738 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "" { clk } "NODE_NAME" } "" } } { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.711 ns) 2.738 ns current_state.state2 2 REG LC_X8_Y6_N8 2 " "Info: 2: + IC(0.558 ns) + CELL(0.711 ns) = 2.738 ns; Loc. = LC_X8_Y6_N8; Fanout = 2; REG Node = 'current_state.state2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "1.269 ns" { clk current_state.state2 } "NODE_NAME" } "" } } { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.62 % ) " "Info: Total cell delay = 2.180 ns ( 79.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.558 ns ( 20.38 % ) " "Info: Total interconnect delay = 0.558 ns ( 20.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "2.738 ns" { clk current_state.state2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 current_state.state2 } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.738 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "" { clk } "NODE_NAME" } "" } } { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.711 ns) 2.738 ns current_state.state2 2 REG LC_X8_Y6_N8 2 " "Info: 2: + IC(0.558 ns) + CELL(0.711 ns) = 2.738 ns; Loc. = LC_X8_Y6_N8; Fanout = 2; REG Node = 'current_state.state2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "1.269 ns" { clk current_state.state2 } "NODE_NAME" } "" } } { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.62 % ) " "Info: Total cell delay = 2.180 ns ( 79.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.558 ns ( 20.38 % ) " "Info: Total interconnect delay = 0.558 ns ( 20.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "2.738 ns" { clk current_state.state2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 current_state.state2 } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "2.738 ns" { clk current_state.state2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 current_state.state2 } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "2.738 ns" { clk current_state.state2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 current_state.state2 } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "1.040 ns" { current_state.state2 current_state.state2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.040 ns" { current_state.state2 current_state.state2 } { 0.000ns 0.562ns } { 0.000ns 0.478ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "2.738 ns" { clk current_state.state2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 current_state.state2 } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "2.738 ns" { clk current_state.state2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 current_state.state2 } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "" { current_state.state2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { current_state.state2 } {  } {  } } } { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 15 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "current_state.state1 enable clk 5.823 ns register " "Info: tsu for register \"current_state.state1\" (data pin = \"enable\", clock pin = \"clk\") is 5.823 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.524 ns + Longest pin register " "Info: + Longest pin to register delay is 8.524 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns enable 1 PIN PIN_143 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_143; Fanout = 5; PIN Node = 'enable'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "" { enable } "NODE_NAME" } "" } } { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.182 ns) + CELL(0.867 ns) 8.524 ns current_state.state1 2 REG LC_X8_Y6_N5 3 " "Info: 2: + IC(6.182 ns) + CELL(0.867 ns) = 8.524 ns; Loc. = LC_X8_Y6_N5; Fanout = 3; REG Node = 'current_state.state1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "7.049 ns" { enable current_state.state1 } "NODE_NAME" } "" } } { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.342 ns ( 27.48 % ) " "Info: Total cell delay = 2.342 ns ( 27.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.182 ns ( 72.52 % ) " "Info: Total interconnect delay = 6.182 ns ( 72.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "8.524 ns" { enable current_state.state1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.524 ns" { enable enable~out0 current_state.state1 } { 0.000ns 0.000ns 6.182ns } { 0.000ns 1.475ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.738 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "" { clk } "NODE_NAME" } "" } } { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.711 ns) 2.738 ns current_state.state1 2 REG LC_X8_Y6_N5 3 " "Info: 2: + IC(0.558 ns) + CELL(0.711 ns) = 2.738 ns; Loc. = LC_X8_Y6_N5; Fanout = 3; REG Node = 'current_state.state1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "1.269 ns" { clk current_state.state1 } "NODE_NAME" } "" } } { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.62 % ) " "Info: Total cell delay = 2.180 ns ( 79.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.558 ns ( 20.38 % ) " "Info: Total interconnect delay = 0.558 ns ( 20.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "2.738 ns" { clk current_state.state1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 current_state.state1 } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "8.524 ns" { enable current_state.state1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.524 ns" { enable enable~out0 current_state.state1 } { 0.000ns 0.000ns 6.182ns } { 0.000ns 1.475ns 0.867ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sample" "UNKNOWN" "V1" "F:/young_ys/zhsj/zonghesheji/young_ys/sample/db/sample.quartus_db" { Floorplan "F:/young_ys/zhsj/zonghesheji/young_ys/sample/" "" "2.738 ns" { clk current_state.state1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 current_state.state1 } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}