sample.tan.qmsg

运行在FPGA上的Verilog程序(实现对ADC的控制)...

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jan 07 09:38:12 2007 " "Info: Processing started: Sun Jan 07 09:38:12 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off sample -c sample --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sample -c sample --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTAN_COMB_LATCH_NODE" "dataOut\[0\]\$latch " "Warning: Node \"dataOut\[0\]\$latch\" is a latch" {  } { { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 12 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "dataOut\[1\]\$latch " "Warning: Node \"dataOut\[1\]\$latch\" is a latch" {  } { { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 12 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "dataOut\[2\]\$latch " "Warning: Node \"dataOut\[2\]\$latch\" is a latch" {  } { { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 12 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "dataOut\[3\]\$latch " "Warning: Node \"dataOut\[3\]\$latch\" is a latch" {  } { { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 12 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "dataOut\[4\]\$latch " "Warning: Node \"dataOut\[4\]\$latch\" is a latch" {  } { { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 12 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "dataOut\[5\]\$latch " "Warning: Node \"dataOut\[5\]\$latch\" is a latch" {  } { { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 12 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "dataOut\[6\]\$latch " "Warning: Node \"dataOut\[6\]\$latch\" is a latch" {  } { { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 12 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "dataOut\[7\]\$latch " "Warning: Node \"dataOut\[7\]\$latch\" is a latch" {  } { { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 12 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}