sample.hier_info

运行在FPGA上的Verilog程序(实现对ADC的控制)...

|sample
clk => current_state~5.IN1
enable => current_state~0.OUTPUTSELECT
enable => current_state~1.OUTPUTSELECT
enable => current_state~2.OUTPUTSELECT
enable => current_state~3.OUTPUTSELECT
enable => current_state~4.OUTPUTSELECT
reset => current_state~6.IN1
dataIn[0] => dataOut[0]$latch.DATAIN
dataIn[1] => dataOut[1]$latch.DATAIN
dataIn[2] => dataOut[2]$latch.DATAIN
dataIn[3] => dataOut[3]$latch.DATAIN
dataIn[4] => dataOut[4]$latch.DATAIN
dataIn[5] => dataOut[5]$latch.DATAIN
dataIn[6] => dataOut[6]$latch.DATAIN
dataIn[7] => dataOut[7]$latch.DATAIN
EOC => next_state.state3.DATAB
EOC => next_state.state2.IN2
ALE <= current_state.state1.DB_MAX_OUTPUT_PORT_TYPE
START <= current_state.state1.DB_MAX_OUTPUT_PORT_TYPE
OE <= OE~0.DB_MAX_OUTPUT_PORT_TYPE
ADDA <= <VCC>
dataOut[0] <= dataOut[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
dataOut[1] <= dataOut[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
dataOut[2] <= dataOut[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
dataOut[3] <= dataOut[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
dataOut[4] <= dataOut[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
dataOut[5] <= dataOut[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
dataOut[6] <= dataOut[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
dataOut[7] <= dataOut[7]$latch.DB_MAX_OUTPUT_PORT_TYPE
dataINT <= current_state.state4.DB_MAX_OUTPUT_PORT_TYPE