sample.map.summary

来自「运行在FPGA上的Verilog程序(实现对ADC的控制)...」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Sun Jan 07 09:37:57 2007
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : sample
Top-level Entity Name : sample
Family : Cyclone
Total logic elements : 14
Total pins : 25
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0