lpc_if.v

LPC总线从设备的verilog设计,包含状态机和中断功能。

//                              -*- Mode: Verilog -*-
// Filename        : lpc_if.v
// Description     : Top file of LPC I/F module
// Author          : James Rao
// Created On      : Thu Dec 18 17:12:52 2008
// Last Modified By: .
// Last Modified On: .
//--------------------------------------------------------------------------------
// Copyright (c) by Kontron (China) Ltd. This model is the confidential and
// proprietary property of Kontron Ltd. And the possession or use of this
// file requires a written license from Kontron (China) Ltd.
//--------------------------------------------------------------------------------
// Update Count    : 0
// Status          : Unknown, Use with caution!
//
// Updata History  :
// Version     Date        Author      Description
//   0.1   2008-12-18    James Rao   Initial design

`include "../define.v"

module lpc_if (/*AUTOARG*/
   // Outputs
   serirq_en, serirq_out, lad_out_en, lad_out, csr_ren, csr_wen, 
   csr_din, csr_offset, bios_post_wr, led_test_wr, 
   // Inputs
   lreset_n, lclk, lframe_n, lad_in, serirq_in, csr_led, csr_uart_0, 
   csr_uart_1, csr_uart_2, csr_uart_3, csr_uart_4, csr_uart_5, 
   csr_uart_6, csr_uart_7, uart_sel, csr_irq_num, irq
   ) ;

   //1. LPC interface.
   input 			 lreset_n;
   input 			 lclk;

   input 			 lframe_n;
   input [3:0] 			 lad_in;
   input 			 serirq_in;   

   output 			 serirq_en;
   output 			 serirq_out;
   
   output 			 lad_out_en;
   output [3:0] 		 lad_out;
   
   //2. interface with CSR.
   input [7:0] 			 csr_led;
   input [7:0] 			 csr_uart_0;
   input [7:0] 			 csr_uart_1;
   input [7:0] 			 csr_uart_2;
   input [7:0] 			 csr_uart_3;
   input [7:0] 			 csr_uart_4;
   input [7:0] 			 csr_uart_5;
   input [7:0] 			 csr_uart_6;
   input [7:0] 			 csr_uart_7;

   input [2:0] 			 uart_sel;
   input [4:0] 			 csr_irq_num;//interrupt line assigned.

   input 			 irq; // interrupt signal from UARTs.

   output 			 csr_ren;   
   output 			 csr_wen;
   output [7:0] 		 csr_din;
   output [3:0] 		 csr_offset;

   output 			 bios_post_wr;
   output 			 led_test_wr;

   reg [7:0] 			 csr_dout;
   
   lpc_fsm
     inst_lpc_fsm (
		   // Outputs
		   .lad_out_en		(lad_out_en),
		   .lad_out		(lad_out),
		   .csr_ren		(csr_ren),
		   .csr_wen		(csr_wen),
		   .csr_din		(csr_din),
		   .csr_offset		(csr_offset),
		   .bios_post_wr	(bios_post_wr),
		   .led_test_wr		(led_test_wr),
		   // Inputs
		   .reset_n		(lreset_n),
		   .clk			(lclk),
		   .lframe_n		(lframe_n),
		   .lad_in		(lad_in),
		   .csr_dout		(csr_dout));

   serirq_fsm
     inst_serirq_fsm (
		      // Outputs
		      .serirq_en	(serirq_en),
		      .serirq_out	(serirq_out),
		      // Inputs
		      .reset_n		(lreset_n),
		      .clk		(lclk),
		      .serirq_in	(serirq_in),
		      .csr_irq_num	(csr_irq_num),
		      .irq		(irq));

   
   always @(/*AUTOSENSE*/csr_led or csr_offset or csr_uart_0
	    or csr_uart_1 or csr_uart_2 or csr_uart_3 or csr_uart_4
	    or csr_uart_5 or csr_uart_6 or csr_uart_7 or uart_sel) begin
      if (csr_offset[3])
	csr_dout = csr_led;
      else begin
	 case (uart_sel)
	   3'b000: csr_dout = csr_uart_0;
	   3'b001: csr_dout = csr_uart_1;
	   3'b010: csr_dout = csr_uart_2;
	   3'b011: csr_dout = csr_uart_3;
	   3'b100: csr_dout = csr_uart_4;
	   3'b101: csr_dout = csr_uart_5;
	   3'b110: csr_dout = csr_uart_6;
	   3'b111: csr_dout = csr_uart_7;
	   default:csr_dout = 8'hFF;
	 endcase // case(uart_sel)
      end // else: !if(sa_lsb5[3])
   end // always @ (posedge clk or negedge reset_n)   
   

endmodule // ipc_if