_primary.vhd

基于altera系列芯片lvds接口的fpga设计 verilog源码

library verilog;
use verilog.vl_types.all;
entity stratix_ram_internal is
    generic(
        operation_mode  : string  := "single_port";
        ram_block_type  : string  := "M512";
        mixed_port_feed_through_mode: string  := "dont_care";
        port_a_data_width: integer := 16;
        port_b_data_width: integer := 16;
        port_a_address_width: integer := 16;
        port_b_address_width: integer := 16;
        port_a_byte_enable_mask_width: integer := 16;
        port_b_byte_enable_mask_width: integer := 16;
        init_file_layout: string  := "port_a";
        port_a_first_address: integer := 0;
        port_a_last_address: integer := 4096;
        port_b_first_address: integer := 0;
        port_b_last_address: integer := 4096;
        mem1            : integer := 0;
        mem2            : integer := 0;
        mem3            : integer := 0;
        mem4            : integer := 0;
        mem5            : integer := 0;
        mem6            : integer := 0;
        mem7            : integer := 0;
        mem8            : integer := 0;
        mem9            : integer := 0
    );
    port(
        port_a_write_enable: in     vl_logic;
        port_b_write_enable: in     vl_logic;
        port_a_data_in  : in     vl_logic_vector(143 downto 0);
        port_b_data_in  : in     vl_logic_vector(143 downto 0);
        port_a_address  : in     vl_logic_vector(15 downto 0);
        port_b_address  : in     vl_logic_vector(15 downto 0);
        port_a_byte_ena_mask: in     vl_logic_vector(15 downto 0);
        port_b_byte_ena_mask: in     vl_logic_vector(15 downto 0);
        port_b_read_enable: in     vl_logic;
        port_a_clock    : in     vl_logic;
        port_b_clock    : in     vl_logic;
        same_clock      : in     vl_logic;
        port_a_data_out : out    vl_logic_vector(143 downto 0);
        port_b_data_out : out    vl_logic_vector(143 downto 0)
    );
end stratix_ram_internal;