2fsk_final.fit.rpt

来自「全数字fsk调制解调的实现 verilog源码」· RPT 代码 · 共 755 行 · 第 1/5 页

Fitter report for 2fsk_final
Wed Oct 29 09:10:58 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Input Pins
  6. Output Pins
  7. All Package Pins
  8. Control Signals
  9. Global & Other Fast Signals
 10. Carry Chains
 11. Embedded Cells
 12. Non-Global High Fan-Out Signals
 13. Peripheral Signals
 14. LAB
 15. Local Routing Interconnect
 16. LAB External Interconnect
 17. Row Interconnect
 18. LAB Column Interconnect
 19. LAB Column Interconnect
 20. Fitter Resource Usage Summary
 21. Fitter Resource Utilization by Entity
 22. Delay Chain Summary
 23. Fitter RAM Summary
 24. Pin-Out File
 25. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------+
; Fitter Summary                                                  ;
+-----------------------+-----------------------------------------+
; Fitter Status         ; Successful - Wed Oct 29 09:10:57 2008   ;
; Quartus II Version    ; 7.2 Build 151 09/26/2007 SJ Web Edition ;
; Revision Name         ; 2fsk_final                              ;
; Top-level Entity Name ; 2fsk_final                              ;
; Family                ; ACEX1K                                  ;
; Device                ; EP1K30TC144-3                           ;
; Timing Models         ; Final                                   ;
; Total logic elements  ; 194 / 1,728 ( 11 % )                    ;
; Total pins            ; 26 / 102 ( 25 % )                       ;
; Total memory bits     ; 256 / 24,576 ( 1 % )                    ;
; Total PLLs            ; 0                                       ;
+-----------------------+-----------------------------------------+


+------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                      ;
+------------------------------------------------------------+--------------------+--------------------+
; Option                                                     ; Setting            ; Default Value      ;
+------------------------------------------------------------+--------------------+--------------------+
; Device                                                     ; EP1K30TC144-3      ;                    ;
; Fitter Effort                                              ; Standard Fit       ; Auto Fit           ;
; Use smart compilation                                      ; Off                ; Off                ;
; Use TimeQuest Timing Analyzer                              ; Off                ; Off                ;
; Router Timing Optimization Level                           ; Normal             ; Normal             ;
; Placement Effort Multiplier                                ; 1.0                ; 1.0                ;
; Router Effort Multiplier                                   ; 1.0                ; 1.0                ;
; Equivalent RAM and MLAB Paused Read Capabilities           ; Care               ; Care               ;
; Optimize Timing                                            ; Normal compilation ; Normal compilation ;
; Optimize IOC Register Placement for Timing                 ; On                 ; On                 ;
; Limit to One Fitting Attempt                               ; Off                ; Off                ;
; Final Placement Optimizations                              ; Automatically      ; Automatically      ;
; Fitter Aggressive Routability Optimizations                ; Automatically      ; Automatically      ;
; Fitter Initial Placement Seed                              ; 1                  ; 1                  ;
; Slow Slew Rate                                             ; Off                ; Off                ;
; PCI I/O                                                    ; Off                ; Off                ;
; Auto Global Memory Control Signals                         ; Off                ; Off                ;
; Logic Cell Insertion - Individual Logic Cells              ; On                 ; On                 ;
; Logic Cell Insertion - I/Os Fed By Carry or Cascade Chains ; On                 ; On                 ;
; Auto Global Clock                                          ; On                 ; On                 ;
; Auto Global Output Enable                                  ; On                 ; On                 ;
; Auto Global Register Control Signals                       ; On                 ; On                 ;
+------------------------------------------------------------+--------------------+--------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Passive Serial           ;
; nWS, nRS, nCS, CS                            ; Unreserved               ;
; RDYnBUSY                                     ; Unreserved               ;
; Data[7..1]                                   ; Unreserved               ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                               ;
+--------+-------+-----+------+---------+--------+--------------+-------------------------+---------------+-----------------+---------------+--------------+
; Name   ; Pin # ; Row ; Col. ; Fan-Out ; Global ; I/O Register ; Use Local Routing Input ; Power Up High ; PCI I/O Enabled ; Single-Pin CE ; I/O Standard ;
+--------+-------+-----+------+---------+--------+--------------+-------------------------+---------------+-----------------+---------------+--------------+
; din[7] ; 102   ;  A  ; --   ; 1       ; no     ; no           ; no                      ; no            ; no              ; no            ; LVTTL/LVCMOS ;
; clk    ; 55    ; --  ; --   ; 6       ; yes    ; no           ; no                      ; no            ; no              ; no            ; LVTTL/LVCMOS ;
; din[6] ; 101   ;  A  ; --   ; 0       ; no     ; no           ; no                      ; no            ; no              ; no            ; LVTTL/LVCMOS ;
; din[5] ; 100   ;  A  ; --   ; 0       ; no     ; no           ; no                      ; no            ; no              ; no            ; LVTTL/LVCMOS ;
; din[4] ; 99    ;  B  ; --   ; 0       ; no     ; no           ; no                      ; no            ; no              ; no            ; LVTTL/LVCMOS ;
; din[3] ; 98    ;  B  ; --   ; 0       ; no     ; no           ; no                      ; no            ; no              ; no            ; LVTTL/LVCMOS ;
; din[2] ; 97    ;  C  ; --   ; 0       ; no     ; no           ; no                      ; no            ; no              ; no            ; LVTTL/LVCMOS ;
; din[1] ; 96    ;  C  ; --   ; 0       ; no     ; no           ; no                      ; no            ; no              ; no            ; LVTTL/LVCMOS ;
; din[0] ; 95    ;  C  ; --   ; 0       ; no     ; no           ; no                      ; no            ; no              ; no            ; LVTTL/LVCMOS ;
+--------+-------+-----+------+---------+--------+--------------+-------------------------+---------------+-----------------+---------------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                          ;
+--------+-------+-----+------+--------------+--------------------------+---------------+----------------+-----------------+---------------+---------------+------------+---------------+--------------+
; Name   ; Pin # ; Row ; Col. ; I/O Register ; Use Local Routing Output ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Single-Pin OE ; Single-Pin CE ; Open Drain ; TRI Primitive ; I/O Standard ;
+--------+-------+-----+------+--------------+--------------------------+---------------+----------------+-----------------+---------------+---------------+------------+---------------+--------------+
; rd     ; 110   ; --  ; 2    ; no           ; no                       ; no            ; no             ; no              ; no            ; no            ; no         ; no            ; LVTTL/LVCMOS ;
; mout   ; 14    ;  C  ; --   ; no           ; no                       ; no            ; no             ; no              ; no            ; no            ; no         ; no            ; LVTTL/LVCMOS ;
; bsyn   ; 13    ;  C  ; --   ; no           ; no                       ; no            ; no             ; no              ; no            ; no            ; no         ; no            ; LVTTL/LVCMOS ;
; lpf    ; 11    ;  C  ; --   ; no           ; no                       ; no            ; no             ; no              ; no            ; no            ; no         ; no            ; LVTTL/LVCMOS ;
; dout1  ; 17    ;  C  ; --   ; no           ; no                       ; no            ; no             ; no              ; no            ; no            ; no         ; no            ; LVTTL/LVCMOS ;
; zx     ; 8     ;  A  ; --   ; no           ; no                       ; no            ; no             ; no              ; no            ; no            ; no         ; no            ; LVTTL/LVCMOS ;
; wf     ; 9     ;  B  ; --   ; no           ; no                       ; no            ; no             ; no              ; no            ; no            ; no         ; no            ; LVTTL/LVCMOS ;
; pulse  ; 10    ;  B  ; --   ; no           ; no                       ; no            ; no             ; no              ; no            ; no            ; no         ; no            ; LVTTL/LVCMOS ;
; div64  ; 72    ; --  ; 3    ; no           ; no                       ; no            ; no             ; no              ; no            ; no            ; no         ; no            ; LVTTL/LVCMOS ;