ps2.tan.qmsg

使用verilog

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 70 " "Warning: Circuit may not operate. Detected 70 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "data_scanC:inst\|started convert:inst1\|tmpASCII\[1\] clk 10.282 ns " "Info: Found hold time violation between source  pin or register \"data_scanC:inst\|started\" and destination pin or register \"convert:inst1\|tmpASCII\[1\]\" for clock \"clk\" (Hold time is 10.282 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "15.715 ns + Largest " "Info: + Largest clock skew is 15.715 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 25.310 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 25.310 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 6 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "" { clk } "NODE_NAME" } "" } } { "PS2.bdf" "" { Schematic "D:/Verilog_PS2_1c12/PS2.bdf" { { 360 -128 40 376 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns lpm_counter0:inst5\|lpm_counter:lpm_counter_component\|cntr_69d:auto_generated\|safe_q\[0\] 2 REG LC_X10_Y5_N1 19 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y5_N1; Fanout = 19; REG Node = 'lpm_counter0:inst5\|lpm_counter:lpm_counter_component\|cntr_69d:auto_generated\|safe_q\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "3.032 ns" { clk lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "db/cntr_69d.tdf" "" { Text "D:/Verilog_PS2_1c12/db/cntr_69d.tdf" 98 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.482 ns) + CELL(1.294 ns) 9.971 ns data_scanC:inst\|started 3 REG LC_X12_Y7_N2 59 " "Info: 3: + IC(4.482 ns) + CELL(1.294 ns) = 9.971 ns; Loc. = LC_X12_Y7_N2; Fanout = 59; REG Node = 'data_scanC:inst\|started'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "5.776 ns" { lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|started } "NODE_NAME" } "" } } { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.273 ns) + CELL(0.511 ns) 12.755 ns data_scanC:inst\|data\[1\]~673 4 COMB LC_X12_Y6_N7 23 " "Info: 4: + IC(2.273 ns) + CELL(0.511 ns) = 12.755 ns; Loc. = LC_X12_Y6_N7; Fanout = 23; COMB Node = 'data_scanC:inst\|data\[1\]~673'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "2.784 ns" { data_scanC:inst|started data_scanC:inst|data[1]~673 } "NODE_NAME" } "" } } { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.033 ns) + CELL(0.914 ns) 15.702 ns convert:inst1\|reduce_or~1303 5 COMB LC_X12_Y7_N7 1 " "Info: 5: + IC(2.033 ns) + CELL(0.914 ns) = 15.702 ns; Loc. = LC_X12_Y7_N7; Fanout = 1; COMB Node = 'convert:inst1\|reduce_or~1303'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "2.947 ns" { data_scanC:inst|data[1]~673 convert:inst1|reduce_or~1303 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.717 ns) + CELL(0.740 ns) 17.159 ns convert:inst1\|reduce_or~1305 6 COMB LC_X12_Y7_N5 1 " "Info: 6: + IC(0.717 ns) + CELL(0.740 ns) = 17.159 ns; Loc. = LC_X12_Y7_N5; Fanout = 1; COMB Node = 'convert:inst1\|reduce_or~1305'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "1.457 ns" { convert:inst1|reduce_or~1303 convert:inst1|reduce_or~1305 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.784 ns) + CELL(0.511 ns) 18.454 ns convert:inst1\|reduce_or~1307 7 COMB LC_X12_Y7_N0 1 " "Info: 7: + IC(0.784 ns) + CELL(0.511 ns) = 18.454 ns; Loc. = LC_X12_Y7_N0; Fanout = 1; COMB Node = 'convert:inst1\|reduce_or~1307'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "1.295 ns" { convert:inst1|reduce_or~1305 convert:inst1|reduce_or~1307 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.220 ns) + CELL(0.511 ns) 20.185 ns convert:inst1\|reduce_or~1308 8 COMB LC_X11_Y7_N8 7 " "Info: 8: + IC(1.220 ns) + CELL(0.511 ns) = 20.185 ns; Loc. = LC_X11_Y7_N8; Fanout = 7; COMB Node = 'convert:inst1\|reduce_or~1308'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "1.731 ns" { convert:inst1|reduce_or~1307 convert:inst1|reduce_or~1308 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.925 ns) + CELL(0.200 ns) 25.310 ns convert:inst1\|tmpASCII\[1\] 9 REG LC_X12_Y10_N4 2 " "Info: 9: + IC(4.925 ns) + CELL(0.200 ns) = 25.310 ns; Loc. = LC_X12_Y10_N4; Fanout = 2; REG Node = 'convert:inst1\|tmpASCII\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "5.125 ns" { convert:inst1|reduce_or~1308 convert:inst1|tmpASCII[1] } "NODE_NAME" } "" } } { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.138 ns ( 28.20 % ) " "Info: Total cell delay = 7.138 ns ( 28.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "18.172 ns ( 71.80 % ) " "Info: Total interconnect delay = 18.172 ns ( 71.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "25.310 ns" { clk lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|started data_scanC:inst|data[1]~673 convert:inst1|reduce_or~1303 convert:inst1|reduce_or~1305 convert:inst1|reduce_or~1307 convert:inst1|reduce_or~1308 convert:inst1|tmpASCII[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "25.310 ns" { clk clk~combout lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|started data_scanC:inst|data[1]~673 convert:inst1|reduce_or~1303 convert:inst1|reduce_or~1305 convert:inst1|reduce_or~1307 convert:inst1|reduce_or~1308 convert:inst1|tmpASCII[1] } { 0.000ns 0.000ns 1.738ns 4.482ns 2.273ns 2.033ns 0.717ns 0.784ns 1.220ns 4.925ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.511ns 0.914ns 0.740ns 0.511ns 0.511ns 0.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.595 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 9.595 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 6 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "" { clk } "NODE_NAME" } "" } } { "PS2.bdf" "" { Schematic "D:/Verilog_PS2_1c12/PS2.bdf" { { 360 -128 40 376 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns lpm_counter0:inst5\|lpm_counter:lpm_counter_component\|cntr_69d:auto_generated\|safe_q\[0\] 2 REG LC_X10_Y5_N1 19 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y5_N1; Fanout = 19; REG Node = 'lpm_counter0:inst5\|lpm_counter:lpm_counter_component\|cntr_69d:auto_generated\|safe_q\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "3.032 ns" { clk lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "db/cntr_69d.tdf" "" { Text "D:/Verilog_PS2_1c12/db/cntr_69d.tdf" 98 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.482 ns) + CELL(0.918 ns) 9.595 ns data_scanC:inst\|started 3 REG LC_X12_Y7_N2 59 " "Info: 3: + IC(4.482 ns) + CELL(0.918 ns) = 9.595 ns; Loc. = LC_X12_Y7_N2; Fanout = 59; REG Node = 'data_scanC:inst\|started'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "5.400 ns" { lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|started } "NODE_NAME" } "" } } { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 35.17 % ) " "Info: Total cell delay = 3.375 ns ( 35.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.220 ns ( 64.83 % ) " "Info: Total interconnect delay = 6.220 ns ( 64.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "9.595 ns" { clk lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|started } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.595 ns" { clk clk~combout lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|started } { 0.000ns 0.000ns 1.738ns 4.482ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "25.310 ns" { clk lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|started data_scanC:inst|data[1]~673 convert:inst1|reduce_or~1303 convert:inst1|reduce_or~1305 convert:inst1|reduce_or~1307 convert:inst1|reduce_or~1308 convert:inst1|tmpASCII[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "25.310 ns" { clk clk~combout lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|started data_scanC:inst|data[1]~673 convert:inst1|reduce_or~1303 convert:inst1|reduce_or~1305 convert:inst1|reduce_or~1307 convert:inst1|reduce_or~1308 convert:inst1|tmpASCII[1] } { 0.000ns 0.000ns 1.738ns 4.482ns 2.273ns 2.033ns 0.717ns 0.784ns 1.220ns 4.925ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.511ns 0.914ns 0.740ns 0.511ns 0.511ns 0.200ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "9.595 ns" { clk lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|started } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.595 ns" { clk clk~combout lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|started } { 0.000ns 0.000ns 1.738ns 4.482ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.057 ns - Shortest register register " "Info: - Shortest register to register delay is 5.057 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_scanC:inst\|started 1 REG LC_X12_Y7_N2 59 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y7_N2; Fanout = 59; REG Node = 'data_scanC:inst\|started'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "" { data_scanC:inst|started } "NODE_NAME" } "" } } { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.411 ns) + CELL(0.740 ns) 3.151 ns convert:inst1\|Select~12146 2 COMB LC_X11_Y10_N2 1 " "Info: 2: + IC(2.411 ns) + CELL(0.740 ns) = 3.151 ns; Loc. = LC_X11_Y10_N2; Fanout = 1; COMB Node = 'convert:inst1\|Select~12146'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "3.151 ns" { data_scanC:inst|started convert:inst1|Select~12146 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.166 ns) + CELL(0.740 ns) 5.057 ns convert:inst1\|tmpASCII\[1\] 3 REG LC_X12_Y10_N4 2 " "Info: 3: + IC(1.166 ns) + CELL(0.740 ns) = 5.057 ns; Loc. = LC_X12_Y10_N4; Fanout = 2; REG Node = 'convert:inst1\|tmpASCII\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "1.906 ns" { convert:inst1|Select~12146 convert:inst1|tmpASCII[1] } "NODE_NAME" } "" } } { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.480 ns ( 29.27 % ) " "Info: Total cell delay = 1.480 ns ( 29.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.577 ns ( 70.73 % ) " "Info: Total interconnect delay = 3.577 ns ( 70.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "5.057 ns" { data_scanC:inst|started convert:inst1|Select~12146 convert:inst1|tmpASCII[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.057 ns" { data_scanC:inst|started convert:inst1|Select~12146 convert:inst1|tmpASCII[1] } { 0.000ns 2.411ns 1.166ns } { 0.000ns 0.740ns 0.740ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 21 -1 0 } } { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "25.310 ns" { clk lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|started data_scanC:inst|data[1]~673 convert:inst1|reduce_or~1303 convert:inst1|reduce_or~1305 convert:inst1|reduce_or~1307 convert:inst1|reduce_or~1308 convert:inst1|tmpASCII[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "25.310 ns" { clk clk~combout lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|started data_scanC:inst|data[1]~673 convert:inst1|reduce_or~1303 convert:inst1|reduce_or~1305 convert:inst1|reduce_or~1307 convert:inst1|reduce_or~1308 convert:inst1|tmpASCII[1] } { 0.000ns 0.000ns 1.738ns 4.482ns 2.273ns 2.033ns 0.717ns 0.784ns 1.220ns 4.925ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.511ns 0.914ns 0.740ns 0.511ns 0.511ns 0.200ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "9.595 ns" { clk lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|started } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.595 ns" { clk clk~combout lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|started } { 0.000ns 0.000ns 1.738ns 4.482ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "5.057 ns" { data_scanC:inst|started convert:inst1|Select~12146 convert:inst1|tmpASCII[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.057 ns" { data_scanC:inst|started convert:inst1|Select~12146 convert:inst1|tmpASCII[1] } { 0.000ns 2.411ns 1.166ns } { 0.000ns 0.740ns 0.740ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "data_scanC:inst\|tmp\[1\] reset clk -1.304 ns register " "Info: tsu for register \"data_scanC:inst\|tmp\[1\]\" (data pin = \"reset\", clock pin = \"clk\") is -1.304 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.958 ns + Longest pin register " "Info: + Longest pin to register delay is 7.958 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns reset 1 PIN PIN_93 24 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_93; Fanout = 24; PIN Node = 'reset'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "" { reset } "NODE_NAME" } "" } } { "PS2.bdf" "" { Schematic "D:/Verilog_PS2_1c12/PS2.bdf" { { 168 -112 56 184 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.071 ns) + CELL(0.914 ns) 4.117 ns data_scanC:inst\|Decoder~226 2 COMB LC_X13_Y6_N5 5 " "Info: 2: + IC(2.071 ns) + CELL(0.914 ns) = 4.117 ns; Loc. = LC_X13_Y6_N5; Fanout = 5; COMB Node = 'data_scanC:inst\|Decoder~226'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "2.985 ns" { reset data_scanC:inst|Decoder~226 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.814 ns) + CELL(0.511 ns) 5.442 ns data_scanC:inst\|Decoder~227 3 COMB LC_X13_Y6_N8 2 " "Info: 3: + IC(0.814 ns) + CELL(0.511 ns) = 5.442 ns; Loc. = LC_X13_Y6_N8; Fanout = 2; COMB Node = 'data_scanC:inst\|Decoder~227'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "1.325 ns" { data_scanC:inst|Decoder~226 data_scanC:inst|Decoder~227 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.925 ns) + CELL(0.591 ns) 7.958 ns data_scanC:inst\|tmp\[1\] 4 REG LC_X12_Y6_N0 29 " "Info: 4: + IC(1.925 ns) + CELL(0.591 ns) = 7.958 ns; Loc. = LC_X12_Y6_N0; Fanout = 29; REG Node = 'data_scanC:inst\|tmp\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "2.516 ns" { data_scanC:inst|Decoder~227 data_scanC:inst|tmp[1] } "NODE_NAME" } "" } } { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.148 ns ( 39.56 % ) " "Info: Total cell delay = 3.148 ns ( 39.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.810 ns ( 60.44 % ) " "Info: Total interconnect delay = 4.810 ns ( 60.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "7.9