control.v

精通verilog HDL语言编程的一个不错的cpu 代码

	`timescale 1ns/10ps
	module control(//input 
 			nrst,clk,
			exe_program,mem_dout,
			rega2ctl,regb2ctl,

			//output

			ctl_wen,
			ctl_din,ctl_addr,
			rega_sel,regb_sel,regc_sel,
			data2reg,curnt_state,
			reg_add,reg_sub,reg_and,reg_or,
			reg_shl,reg_shr,direct,reg_unchg,
			reg_anm,reg_orm
					);
			
			input nrst,clk;
			input exe_program;
			input[7:0] mem_dout;
			input[7:0] rega2ctl,regb2ctl;

			output   ctl_wen;
			output[7:0] ctl_din,ctl_addr;
			output[1:0] rega_sel,regb_sel,regc_sel;
			output[7:0] data2reg;
			output[1:0] curnt_state;
			output 	reg_add,reg_sub,reg_and,reg_or;		
			output reg_shl,reg_shr,direct,reg_unchg;
			output reg_anm,reg_orm;

			reg      ctl_wen,delay_d;
			reg[7:0] pc;

			reg	reg_add,reg_sub,reg_and,reg_or,	reg_anm,reg_orm;
			reg	reg_shl,reg_shr,mem_acc;


	parameter  reset=2'b00,
                   fetch=2'b01,
                   decode=2'b01,
                   execute=2'b11;




	parameter ADD=4'b0000,
                  SUB=4'b0001,
                  ADI=4'b0010,
                  SBI=4'b0011,
                  ANM=4'b0100,
                  ORM=4'b0101,
                  ANP=4'b0110,
                  ORR=4'b0111,
                  SHL=4'b1000,
                  SHR=4'b1001,
                  LBM=4'b1010,
                  SBM=4'b1011,
                  MOV=4'b1100,
                  JEQ=4'b1101,
                  JLS=4'b1110,
                  JMP=4'b1111;


	reg [3:0] instruction;
	reg[1:0] nxt_state,curnt_state;

	reg[1:0] rega_sel,regb_sel,regc_sel;
	reg[7:0] data2reg;
	reg	inc,direct,reg_unchg,delay,abs_jmp;
	reg[7:0] addr_inc;
	wire[7:0] ctl_addr=((curnt_state==execute)&(instruction==SBM))? rega2ctl:
			    ((curnt_state==execute)&(instruction==LBM))? regb2ctl:
			    ((curnt_state==execute)&(instruction==ANM)&~delay_d)? data2reg:
			    ((curnt_state==execute)&(instruction==ORM)&~delay_d)? data2reg:pc;

	wire[7:0] ctl_din=((curnt_state==execute)&(instruction==SBM))? regb2ctl:
			((curnt_state==execute)&(instruction==LBM))? rega2ctl:0;


	always @ (posedge clk or negedge nrst)
	 if (~nrst) curnt_state<=reset;
	 else if (exe_program) curnt_state<=nxt_state;

	always @(curnt_state or mem_dout or instruction or delay_d or rega2ctl or regb2ctl )
	begin 
	 case(curnt_state)
	 reset:begin 
		inc=0;
		regc_sel=0;
		data2reg=0;
		reg_add=0;
		reg_sub=0;
		reg_and=0;
		reg_or=0;
		reg_shl=0;
		reg_shr=0;
		ctl_wen=0;

		reg_unchg=0;
		direct=0;
		delay=0;
		addr_inc=0;
		abs_jmp=0;
		reg_anm=0;
		reg_orm=0;
		nxt_state=fetch;
	      end

	fetch:begin
		inc=1;
		regc_sel=0;
		reg_add=0;
		reg_sub=0;
		reg_and=0;
		reg_or=0;
		reg_shl=0;
		reg_shr=0;
		ctl_wen=1;

		
		direct=0;
		delay=0;
		addr_inc=0;
		abs_jmp=0;
		reg_anm=0;
		reg_orm=0;
		reg_unchg=0;
		data2reg=0;
		case(instruction)
		 LBM:begin
			data2reg=mem_dout;
		     end
		endcase
		nxt_state=decode;
		end
	decode:begin
		inc=0;		
		reg_add=0;
		reg_sub=0;
		reg_and=0;
		reg_or=0;
		reg_shl=0;
		reg_shr=0;
		regc_sel=0;
		ctl_wen=1;
		abs_jmp=0;
		reg_anm=0;
		reg_orm=0;



		reg_unchg=0;
		direct=0;
		delay=0;
		addr_inc=0;
		data2reg=0;

		nxt_state=execute;
		end
	execute: begin
		inc=1;		
		reg_add=0;
		reg_sub=0;
		reg_and=0;
		reg_or=0;
		reg_shl=0;
		reg_shr=0;
		regc_sel=mem_dout[7:6];

		data2reg=mem_dout[7:6];
		ctl_wen=1;
		abs_jmp=0;
		reg_anm=0;
		reg_orm=0;

		reg_unchg=0;
		direct=0;
		delay=0;

		addr_inc=0;
		case(instruction)
		 ADD:begin
			reg_add=1;
			nxt_state=fetch;
			end
		 SUB:begin 
			reg_sub=1;
			nxt_state=fetch;
			end			
		 ADI:begin
			direct=1;
			reg_add=1;
			nxt_state=fetch;
			end	
		 SBI:begin
			direct=1;
			reg_sub=1;
			nxt_state=fetch;
			end
		 ANM:begin
			if (delay_d==1) begin 
			  inc=1;
			  delay=0;
			  reg_unchg=0;
			  reg_anm=1;
			nxt_state=fetch;
			end  else begin
			  inc=0;
			  delay=1;
			  reg_unchg=1; 
			nxt_state=fetch;
				end
		   end
		 ORM:begin
			if (delay_d==1) begin 
			  inc=1;
			  delay=0;
			  reg_unchg=0;
			  reg_orm=1;
			nxt_state=fetch;
			end  else begin
			  inc=0;
			  delay=1;
			  reg_unchg=1; 
			nxt_state=fetch;
				end
		   end

		 ANP:begin
			direct=0;
			reg_and=1;
			nxt_state=fetch;
			end
		 ORR:begin
			direct=0;
			reg_or=1;
			nxt_state=fetch;
			end
		 SHL:begin
			reg_shl=1;
			nxt_state=fetch;
			end
		 SHR:begin
			reg_shr=1;
			nxt_state=fetch;
			end
		 LBM:begin
			if (delay_d==1) begin 
			  inc=1;
			  delay=0;
			  reg_unchg=0;

			nxt_state=fetch;
			end  else begin
			  inc=0;
			  delay=1; 
			nxt_state=fetch;
				end
		   end

		 SBM:begin
			ctl_wen=#1 0;
			  reg_unchg=1;	
			nxt_state=fetch;		
		   end
		 MOV:begin
			nxt_state=fetch;		
		   end

		 JEQ:begin
			reg_unchg=1;
			if (rega2ctl==regb2ctl)
			  begin
			  abs_jmp=1;
			  data2reg=data2reg;
			end  else begin
			  abs_jmp=0;
			  addr_inc=0;
		     end
			nxt_state=fetch;		
		   end
		 JLS:begin
			reg_unchg=1;
			if (rega2ctl<regb2ctl)
			  begin
			  abs_jmp=1;
			  data2reg=data2reg;
			end  else begin
			  abs_jmp=0;
			  addr_inc=0;
		     end
			nxt_state=fetch;		
		   end

		 JMP:begin
			reg_unchg=1;
			abs_jmp=1;		
			nxt_state=fetch;		
		   end
		   
		   
		 default:;
		endcase
	  end
		
		
	    default:begin
			nxt_state=reset;		
		   end
		endcase
	end	   

	always @(posedge clk)
	begin
	 if(!nrst) begin 
	     rega_sel<=0;
	     regb_sel<=0;
		end 
	 else if(curnt_state==decode) begin
		rega_sel<=mem_dout[3:2];
		regb_sel<=mem_dout[1:0];
		end
	end	

	wire get_instr=exe_program & (curnt_state==decode);
	always @(posedge clk or negedge nrst)			
		if(~nrst) pc<=0;
		else if (abs_jmp) pc<=data2reg;
		else if (inc&exe_program) pc<=pc+1+addr_inc;

	always @(posedge clk or negedge nrst)	
		if(~nrst) delay_d<=0;
		else delay_d<=delay;

endmodule