alu.v

精通verilog HDL语言编程的一个不错的cpu 代码

`timescale 1ns/10ps
module alu( //input 
        nrst,clk,
	rega_sel,regb_sel,regc_sel,
	data2reg,curnt_state,
	reg_add,reg_sub,reg_and,reg_or,
	reg_shl,reg_shr,reg_unchg,
        direct,reg_anm,reg_orm,

	//output
	rega2ctl,regb2ctl
	                  );
	input nrst,clk;
	input [1:0] rega_sel,regb_sel,regc_sel;
	input [7:0] data2reg;
	input [1:0] curnt_state;
	input	    reg_add,reg_sub,reg_and,reg_or;
	input	    reg_shl,reg_shr,reg_unchg;
	input       direct,reg_anm,reg_orm;

	output[7:0] rega2ctl,regb2ctl;

	reg[7:0] r0,r1,r2,r3;

        wire sel_r00=(curnt_state==2'b11)&(rega_sel==2'b00);
	wire sel_r01=(curnt_state==2'b11)&(rega_sel==2'b01);
	wire sel_r02=(curnt_state==2'b11)&(rega_sel==2'b10);    	
	wire sel_r03=(curnt_state==2'b11)&(rega_sel==2'b11); 

	wire [7:0] rega=sel_r00 ? r0:
			sel_r01 ? r1:
			sel_r02 ? r2:
			sel_r03 ? r3:0;

	wire[7:0] rega2ctl=rega;
	

        wire sel_r10=(curnt_state==2'b11)&(regb_sel==2'b00);
        wire sel_r11=(curnt_state==2'b11)&(regb_sel==2'b01);
        wire sel_r12=(curnt_state==2'b11)&(regb_sel==2'b10);
        wire sel_r13=(curnt_state==2'b11)&(regb_sel==2'b11);

	wire [7:0] regb=sel_r10 ? r0:
			sel_r11 ? r1:
			sel_r12 ? r2:
			sel_r13 ? r3:0;	

	wire[7:0] regb2ctl=regb;

        wire sel_r20=(curnt_state==2'b11)&(regb_sel==2'b00);
        wire sel_r21=(curnt_state==2'b11)&(regb_sel==2'b01);
        wire sel_r22=(curnt_state==2'b11)&(regb_sel==2'b10);
        wire sel_r23=(curnt_state==2'b11)&(regb_sel==2'b11);

	wire [7:0] regc=sel_r20 ? r0:
			sel_r21 ? r1:
			sel_r22 ? r2:
			sel_r23 ? r3:0;	

	wire [8:0] reg_opion=(~direct & reg_anm)? rega& data2reg:
			(~direct & reg_orm)? rega|data2reg:
			(~direct & reg_shr)? rega>>1:
			(~direct & reg_shl)? rega<<1:
			(~direct & reg_or )? regb|regc:
			(~direct & reg_and)? regb&regc:
			( direct & reg_add)? regb+data2reg:
			( direct & reg_sub)? regb-data2reg:
			(~direct & reg_add)? regb+regc:
			(~direct & reg_sub)? regb-regc:0;


	wire[7:0] data_record=(reg_add|reg_sub|reg_and|reg_anm|reg_or|reg_orm|reg_shr|reg_shl)?
						reg_opion:data2reg;

	always @(posedge clk or negedge nrst)
	if(~nrst) r0<=0;
	else if(reg_unchg) r0<=r0;
	else if(sel_r00) r0<=data_record;

	always @(posedge clk or negedge nrst)
	if(~nrst) r1<=0;
	else if(reg_unchg) r1<=r1;
	else if(sel_r01) r1<=data_record;

	always @(posedge clk or negedge nrst)
	if(~nrst) r2<=0;
	else if(reg_unchg) r2<=r2;
	else if(sel_r02) r2<=data_record;	

	always @(posedge clk or negedge nrst)
	if(~nrst) r3<=0;
	else if(reg_unchg) r3<=r3;
	else if(sel_r03) r3<=data_record;

endmodule