memory.v

来自「精通verilog HDL语言编程的一个不错的cpu 代码」· Verilog 代码 · 共 35 行

	`timescale 1ns/10ps
	`define depth 256
	`define width 8

	module memory(//input 
			CLK,CEN,
			WEN,A,
			D,
 			//output
			Q);

	input CLK,CEN,WEN;
	input[7:0] A;
	input[`width-1:0] D;

	output[`width-1:0] Q;
	
	reg[`width-1:0] mem[0:`depth-1];

	always @(posedge CLK)
	begin 
	 if (~WEN&~CEN) mem[A]<=#1 D;
	end
	
	reg[`width-1:0] rptr;
	always @(posedge CLK) rptr<=#1 A;

	wire[`width-1:0] Q=~CEN? mem[rptr] : 8'bz;

	wire [7:0] memf0=mem[8'hf0];
	wire [7:0] memf1=mem[8'hf1];
	wire [7:0] memf2=mem[8'hf2];
	wire [7:0] memf3=mem[8'hf3];

endmodule