fast_alu_pack.v

用verilog写的

// fast_alu_pack.v

module fast_alu_pack(
	input sgn,			// Sign bit: 0==positive, 1==negative
	input [7:0] exp,	// Exponent with +127 bias
	input [23:0] man,	// Mantissa with binary point between bits 23 and 22
	output [31:0] fp	// IEEE standard single-precision float
);

assign fp = { sgn, exp, (exp < 255) ? (exp > 0) ? man[22:0] : man[23:1] : 23'b0 };

endmodule