sound.v.bak

通过verilog语言

module sound(beep,clk,key_s,led);
    output beep;
    input clk;
    input[8:1] key_s;
    output[7:0] led;

    reg[15:0] counter;
    reg beep;
    reg[8:0] state;
    
    parameter[8:0] IDLE = 9'b000000001 ,
                   DO   = 9'b000000010 ,
                   RE   = 9'b000000100 ,
                   ME   = 9'b000001000 ,
                   FA   = 9'b000010000 ,
                   SO   = 9'b000100000 ,
                   LA   = 9'b001000000 ,
                   SI   = 9'b010000000 ,
                   DOH  = 9'b100000000 ; 
    
    initial beep = 1'b1;
    
    assign led[7:0] = state[7:0];
    
    
    always@(posedge clk)
  
    case(state)
    IDLE:
    begin
        if(key_s[1] == 0) state <= DO;
        else if(key_s[2] == 0) state <= RE;
        else if(key_s[3] == 0) state <= ME;
        else if(key_s[4] == 0) state <= FA;
        else if(key_s[5] == 0) state <= SO;
        else if(key_s[6] == 0) state <= LA;
        else if(key_s[7] == 0) state <= SI;
        else if(key_s[8] == 0) state <= DOH;
        else state <= IDLE;
    end
    
    DO:
    begin
        if(counter >= 16'hBAB9)
        begin
            beep <= ~beep;
            counter <= 0; 
        end
        else
            counter <= counter + 16'h1; 
            
        if(key_s[1] == 1) state <= IDLE;
        else state <= DO;
    end
    
    RE:
    begin
        if(counter >= 16'hA639)
        begin
            beep <= ~beep;
            counter <= 0; 
        end
        else
            counter <= counter + 16'h1; 
            
        if(key_s[2] == 1) state <= IDLE;
        else state <= RE;
    end
    
    ME:
    begin
        if(counter >= 16'h9413)
        begin
            beep <= ~beep;
            counter <= 0; 
        end
        else
            counter <= counter + 16'h1; 
            
        if(key_s[3] == 1) state <= IDLE;
        else state <= ME;
    end
    
    FA:
    begin
        if(counter >= 16'h8BE8)
        begin
            beep <= ~beep;
            counter <= 0; 
        end
        else
            counter <= counter + 16'h1; 
            
        if(key_s[4] == 1) state <= IDLE;
        else state <= FA;
    end
    
    SO:
    begin
        if(counter >= 16'h7C8F)
        begin
            beep <= ~beep;
            counter <= 0; 
        end
        else
            counter <= counter + 16'h1; 
            
        if(key_s[5] == 1) state <= IDLE;
        else state <= SO;
    end
    
    LA:
    begin
        if(counter >= 16'h6EF9)
        begin
            beep <= ~beep;
            counter <= 0; 
        end
        else
            counter <= counter + 16'h1; 
            
        if(key_s[6] == 1) state <= IDLE;
        else state <= LA;
    end
    
    SI:
    begin
        if(counter >= 16'h62E4)
        begin
            beep <= ~beep;
            counter <= 0; 
        end
        else
            counter <= counter + 16'h1; 
            
        if(key_s[7] == 1) state <= IDLE;
        else state <= SI;
    end
    
    DOH:
    begin
        if(counter >= 16'h5D51)
        begin
            beep <= ~beep;
            counter <= 0; 
        end
        else
            counter <= counter + 16'h1; 
            
        if(key_s[8] == 1) state <= IDLE;
        else state <= DOH;
    end
    default:
        state <= IDLE;
        
    endcase
    
    
endmodule