clk_div.vhd

来自「实现对时钟信号的技术分频」· VHDL 代码 · 共 64 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY clk_div IS
     PORT(CLK:IN STD_LOGIC;
         clk_div3:OUT STD_LOGIC);
END clk_div;
  ARCHITECTURE behave OF clk_div IS
	   CONSTANT LD:STD_LOGIC_VECTOR(1 DOWNTO 0):="01";
	   CONSTANT MD:STD_LOGIC_VECTOR(1 DOWNTO 0):="10";
	   CONSTANT ZERO:STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS=>'0');
	   SIGNAL COUNTF:STD_LOGIC_VECTOR(1 DOWNTO 0);
	   SIGNAL COUNTR:STD_LOGIC_VECTOR(1 DOWNTO 0);
       SIGNAL LEVELR:STD_LOGIC;
	   SIGNAL LEVELF:STD_LOGIC;
	BEGIN
      PROCESS(CLK)
         BEGIN 
			IF(CLK'EVENT AND CLK='1')THEN
			   IF(COUNTR=MD)THEN
			   COUNTR<=ZERO;
			   ELSE COUNTR<=COUNTR+1;
			   END IF;
			END IF;
	  END PROCESS;
	 
	 PROCESS(CLK)
         BEGIN 
			IF(CLK'EVENT AND CLK='0')THEN
			   IF(COUNTF=MD)THEN
			   COUNTF<=ZERO;
			   ELSE COUNTF<=COUNTF+1;
			   END IF;
			END IF;
	  END PROCESS;
	
	 PROCESS(CLK)
          BEGIN 
            IF(CLK'EVENT AND CLK='1')THEN
				IF(COUNTR=ZERO)THEN
				LEVELR<='1';
				ELSIF(COUNTR=LD)THEN 
				LEVELR<='0';
				END IF;
			END IF;
	  END PROCESS;
        
     PROCESS(CLK)
          BEGIN 
            IF(CLK'EVENT AND CLK='0')THEN
				IF(COUNTF=ZERO)THEN
				LEVELF<='1';
				ELSIF(COUNTF=LD)THEN 
				LEVELF<='0';
				END IF;
			END IF;
	  END PROCESS;
	
	clk_div3<=LEVELR OR LEVELF;
	END behave;