📄 mac_4_csa.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:57:41 12/19/2008
// Design Name:
// Module Name: MAC_4
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MAC_4(A, //input
B,
C,
O, //output
sum_overflow,
co_overflow
);
input [3:0] A;
input [3:0] B;
input [3:0] C;
output [7:0] O;
output sum_overflow;
output co_overflow;
wire A3,A2,A1,A0;
wire B3,B2,B1,B0;
wire O7,O6,O5,O4,O3,O2,O1,O0;
wire co_overflow;
wire sum_overflow;
//===============================seperate each bit of the HEX value=====================================
assign {A3,A2,A1,A0} = A[3:0];
assign {B3,B2,B1,B0} = B[3:0];
assign {C3,C2,C1,C0} = C[3:0];
assign O[7:0] = {O7,O6,O5,O4,O3,O2,O1,O0};
//==================================column of O0======================================
FA_1 FA_O0_0(.in0 (A0&&B0),
.in1 (1'b0),
.in2 (C0),
.sum (O0),
.co (C10)
);
//==================================column of O1======================================
FA_1 FA_O1_0(.in0 (A1&&B0),
.in1 (1'b0),
.in2 (A0&&B1),
.sum (S10),
.co (C11)
);
FA_1 FA_O1_1(.in0 (S10),
.in1 (C10),
.in2 (C1),
.sum (O1),
.co (C20)
);
//==================================column of O2======================================
FA_1 FA_O2_0(.in0 (A2&&B0),
.in1 (1'b0),
.in2 (A1&&B1),
.sum (S20),
.co (C12)
);
FA_1 FA_O2_1(.in0 (S20),
.in1 (C11),
.in2 (A0&&B2),
.sum (S21),
.co (C21)
);
FA_1 FA_O2_3(.in0 (S21),
.in1 (C20),
.in2 (C2),
.sum (O2),
.co (C30)
);
//==================================column of O3======================================
FA_1 FA_O3_0(.in0 (A3&&(!B0)),
.in1 (1'b0),
.in2 (A2&&B1),
.sum (S30),
.co (C13)
);
FA_1 FA_O3_1(.in0 (S30),
.in1 (C12),
.in2 (A1&&B2),
.sum (S31),
.co (C22)
);
FA_1 FA_O3_2(.in0 (S31),
.in1 (C21),
.in2 ((!A0)&&B3),
.sum (S32),
.co (C31)
);
FA_1 FA_O3_3(.in0 (S32),
.in1 (C30),
.in2 (C3),
.sum (S33),
.co (C40)
);
/*
FA_1 FA_O3_4(.in0 (S33),
.in1 (A3),
.in2 (B3),
.sum (O3),
.co (C50)
);
*/
//==================================column of O4======================================
FA_1 FA_O4_0(.in0 (A3&&(!B1)),
.in1 (C13),
.in2 (A2&&B2),
.sum (S40),
.co (C23)
);
FA_1 FA_O4_1(.in0 (S40),
.in1 (C22),
.in2 ((!A1)&&B3),
.sum (S41),
.co (C32)
);
FA_1 FA_O4_2(.in0 (S41),
.in1 (C31),
.in2 (C3),
.sum (S42),
.co (C41)
);
/*
FA_1 FA_O4_3(.in0 (S42),
.in1 (C40),
.in2 (C50),
.sum (O4),
.co (C51)
);
*/
//==================================column of O5======================================
FA_1 FA_O5_0(.in0 (A3&&(!B2)),
.in1 (C23),
.in2 ((!A2)&&B3),
.sum (S50),
.co (C33)
);
FA_1 FA_O5_1(.in0 (S50),
.in1 (C32),
.in2 (C3),
.sum (S51),
.co (C42)
);
/*
FA_1 FA_O5_2(.in0 (S51),
.in1 (C41),
.in2 (C51),
.sum (O5),
.co (C52)
);
*/
//==================================column of O6======================================
FA_1 FA_O6_0(.in0 (!A3),
.in1 (!B3),
.in2 (A3&&B3),
.sum (S60),
.co (C34)
);
FA_1 FA_O6_1(.in0 (S60),
.in1 (C33),
.in2 (C3),
.sum (S61),
.co (C43)
);
/*
FA_1 FA_O6_2(.in0 (S61),
.in1 (C42),
.in2 (C52),
.sum (O6),
.co (C53)
);
*/
//==================================column of O7======================================
FA_1 FA_O7_0(.in0 (1'b1),
.in1 (C34),
.in2 (C3),
.sum (S70),
.co (C44)
);
/*
FA_1 FA_O7_1(.in0 (S70),
.in1 (C43),
.in2 (C53),
.sum (O7),
.co (C54)
);
*/
//==================================column of overflow======================================
FA_1 FA_O8_0(.in0 (1'b0),
.in1 (C44),
.in2 (C54),
.sum (sum_overflow),
.co (co_overflow)
);
//=========================Carry Select Adder for final add operation=======================
CSA_FINAL CSA_FINAL(.c0 (B3), //input
.x4 (S70),
.x3 (S61),
.x2 (S51),
.x1 (S42),
.x0 (S33),
.y4 (C43),
.y3 (C42),
.y2 (C41),
.y1 (C40),
.y0 (A3),
.s4 (O7), //output
.s3 (O6),
.s2 (O5),
.s1 (O4),
.s0 (O3),
.c5 (C54)
);
endmodule
module FA_1(in0,
in1,
in2,
sum,
co
);
input in0;
input in1;
input in2;
output sum;
output co;
wire sum,co;
assign sum = in0^in1^in2;
assign co = (in0&&in1)||(in0&&in2)||(in1&&in2);
endmodule
module CLA_4(c0, //input
x3,
x2,
x1,
x0,
y3,
y2,
y1,
y0,
s3, //output
s2,
s1,
s0,
c4
);
input c0;
input x3,x2,x1,x0;
input y3,y2,y1,y0;
output s3,s2,s1,s0;
output c4;
wire g0,p0;
wire g1,p1;
wire g2,p2;
wire g3,p3;
wire s0,s1,s2,s3;
// wire c1,c2,c3;
wire c4;
assign g0 = x0&&y0;
assign p0 = x0^y0;
// assign c1 = g0||(p0&&c0);
// assign s0 = p0^c0;
assign g1 = x1&&y1;
assign p1 = x1^y1;
// assign c2 = g1||(p1&&c1);
// assign s1 = p1^c1;
assign g2 = x2&&y2;
assign p2 = x2^y2;
// assign c3 = g2||(p2&&c2);
// assign s2 = p2^c2;
assign g3 = x3&&y3;
assign p3 = x3^y3;
// assign c4 = g3||(p3&&c3);
// assign s3 = p3^c3;
assign s0 = p0^c0;
assign s1 = p1^((p0&&c0) || g0);
assign s2 = p2^((p1&&p0&&c0) || (p1&&g0) || g1);
assign s3 = p3^((p2&&p1&&p0&&c0) || (p2&&p1&&g0) || (p2&&g1) ||g2);
assign c4 = p3&&(p2&&p1&&p0&&c0 || p2&&p1&&g0 || p2&&g1 || g2) || g3;
endmodule
module CSA_FINAL(c0, //input
x4,
x3,
x2,
x1,
x0,
y4,
y3,
y2,
y1,
y0,
s4, //output
s3,
s2,
s1,
s0,
c5
);
input c0;
input x4,x3,x2,x1,x0;
input y4,y3,y2,y1,y0;
output s4,s3,s2,s1,s0;
output c5;
wire s3_temp0,
s2_temp0,
s1_temp0,
s0_temp0,
c4_temp0;
wire s3_temp1,
s2_temp1,
s1_temp1,
s0_temp1,
c4_temp1;
wire s4_temp0,
s4_temp1,
c5_temp0,
c5_temp1;
//==================Carry Select Adder with low 4-bit implemented in CLA =======================
CLA_4 CLA_4_0(.c0 (1'b0), //input
.x3 (x3),
.x2 (x2),
.x1 (x1),
.x0 (x0),
.y3 (y3),
.y2 (y2),
.y1 (y1),
.y0 (y0),
.s3 (s3_temp0), //output
.s2 (s2_temp0),
.s1 (s1_temp0),
.s0 (s0_temp0),
.c4 (c4_temp0)
);
CLA_4 CLA_4_1(.c0 (1'b1), //input
.x3 (x3),
.x2 (x2),
.x1 (x1),
.x0 (x0),
.y3 (y3),
.y2 (y2),
.y1 (y1),
.y0 (y0),
.s3 (s3_temp1), //output
.s2 (s2_temp1),
.s1 (s1_temp1),
.s0 (s0_temp1),
.c4 (c4_temp1)
);
MUX2 MUX2_S0(.in0 (s0_temp0), //input
.in1 (s0_temp1),
.sel (c0),
.out (s0) //output
);
MUX2 MUX2_S1(.in0 (s1_temp0), //input
.in1 (s1_temp1),
.sel (c0),
.out (s1) //output
);
MUX2 MUX2_S2(.in0 (s2_temp0), //input
.in1 (s2_temp1),
.sel (c0),
.out (s2) //output
);
MUX2 MUX2_S3(.in0 (s3_temp0), //input
.in1 (s3_temp1),
.sel (c0),
.out (s3) //output
);
MUX2 MUX2_C4(.in0 (c4_temp0), //input
.in1 (c4_temp1),
.sel (c0),
.out (c4) //output
);
//==========================Carry Select Adder for the last stage---s4 output=============================
FA_1 FA_1_0(.in0 (x4),
.in1 (y4),
.in2 (1'b0),
.sum (s4_temp0),
.co (c5_temp0)
);
FA_1 FA_1_1(.in0 (x4),
.in1 (y4),
.in2 (1'b1),
.sum (s4_temp1),
.co (c5_temp1)
);
MUX2 MUX2_S4(.in0 (s4_temp0), //input
.in1 (s4_temp1),
.sel (c4),
.out (s4) //output
);
MUX2 MUX2_C5(.in0 (c5_temp0), //input
.in1 (c5_temp1),
.sel (c4),
.out (c5) //output
);
endmodule
module MUX2(in0, //input
in1,
sel,
out //output
);
input in0;
input in1;
input sel;
output out;
assign out = sel ? in1:in0;
endmodule⌨️ 快捷键说明
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