time_display.v

用Verilog实现的电子时钟显示器

`timescale  1ms/1ns
module time_display(clk,rst,sec,min,hour);
  
  output[5:0] sec,min,hour;
  input clk,rst;
  
  reg[5:0] count;
  reg[5:0] sec,min,hour;
    
  always@(posedge clk or negedge rst)
    begin
      if(!rst)
        begin
          count=0; sec=0; min=0; hour=0;
        end 
      else
        count=count+1;
        
      if(count==60)
        #8
        begin
          sec=sec+1;count=0;
        end
        
      if(sec==59 && count==59)
        #24
        begin
          min=min+1;sec=0;count=0;
        end 
             
      if(min==59 && sec==59)
        #960
        begin
          hour=hour+1;min=0;sec=0;count=0;
        end
        
      if(hour==23 && min==59 && sec==59)
        #960
        begin
          hour=0;min=0;sec=0;count=0;
        end
    end 
       
endmodule