test.v

来自「用Verilog实现的电子时钟显示器」· Verilog 代码 · 共 55 行

`timescale  1ms/1ns
module test();

  reg rst,clk;
  wire[5:0] sec,min,hour;
  wire[6:0] seg1,seg2,seg3,seg4,seg5,seg6;
    
  time_display uut(clk,rst,sec,min,hour); 
  LED LED1(seg1,sec%6'd10);
  LED LED2(seg2,sec/6'd10);
  LED LED3(seg3,min%6'd10);
  LED LED4(seg4,min/6'd10);
  LED LED5(seg5,hour%6'd10);
  LED LED6(seg6,hour/6'd 10);
  
  initial
    begin
      rst=0;
      #16  rst=1;
      #7200000 $finish;
    end
    
  initial
    clk=0;
    
  always
    begin
      #8 clk=1;
      #8 clk=0;
    end
  
  // Display Results
  initial  // print all changes to all signal values
    begin
      $monitor($time/1000.0, " s  %d  %d  %d  %b  %b  %b  %b  %b  %b", 
                    hour,min,sec,seg6,seg5,seg4,seg3,seg2,seg1);
    end
    
  //Create a simulation database
  initial
  begin
    $shm_open("file.shm");  //Open a waveform database
    $shm_probe("A");  //Probe all nodes in this module
  end 
        
endmodule